llvm.org GIT mirror llvm / 041cde2
Add support for expanding PPC 128 bit floats. For this it is convenient to permit floats to be used with EXTRACT_ELEMENT, so I tweaked things to allow that. I also added libcalls for ppcf128 to i32 forms of FP_TO_XINT, since they exist in libgcc and this case can certainly occur (and does occur in the testsuite) - before the i64 libcall was being used. Also, the XINT_TO_FP result seemed to be wrong when the argument is an i128: the wrong fudge factor was added (the i32 and i64 cases were handled directly, but the i128 code fell through to some generic softening code which seemed to think it was i64 to f32!). So I fixed it by adding a fudge factor that I found in my breakfast cereal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52739 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 12 years ago
6 changed file(s) with 221 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
9898 FPTOSINT_F64_I128,
9999 FPTOSINT_F80_I64,
100100 FPTOSINT_F80_I128,
101 FPTOSINT_PPCF128_I32,
101102 FPTOSINT_PPCF128_I64,
102103 FPTOSINT_PPCF128_I128,
103104 FPTOUINT_F32_I32,
109110 FPTOUINT_F80_I32,
110111 FPTOUINT_F80_I64,
111112 FPTOUINT_F80_I128,
113 FPTOUINT_PPCF128_I32,
112114 FPTOUINT_PPCF128_I64,
113115 FPTOUINT_PPCF128_I128,
114116 SINTTOFP_I32_F32,
192192 CALL,
193193
194194 // EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
195 // a Constant, which is required to be operand #1) half of the integer value
196 // specified as operand #0. This is only for use before legalization, for
197 // values that will be broken into multiple registers.
195 // a Constant, which is required to be operand #1) half of the integer or
196 // float value specified as operand #0. This is only for use before
197 // legalization, for values that will be broken into multiple registers.
198198 EXTRACT_ELEMENT,
199199
200200 // BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. Given
201201 // two values of the same integer value type, this produces a value twice as
202202 // big. Like EXTRACT_ELEMENT, this can only be used before legalization.
203203 BUILD_PAIR,
204
204
205205 // MERGE_VALUES - This node takes multiple discrete operands and returns
206206 // them all as its individual results. This nodes has exactly the same
207207 // number of inputs and outputs, and is only valid before legalization.
117117 RTLIB::ADD_F64,
118118 RTLIB::ADD_F80,
119119 RTLIB::ADD_PPCF128),
120 NVT, Ops, 2, false/*sign irrelevant*/);
120 NVT, Ops, 2, false);
121121 }
122122
123123 SDOperand DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
168168 RTLIB::MUL_F64,
169169 RTLIB::MUL_F80,
170170 RTLIB::MUL_PPCF128),
171 NVT, Ops, 2, false/*sign irrelevant*/);
171 NVT, Ops, 2, false);
172172 }
173173
174174 SDOperand DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
180180 RTLIB::SUB_F64,
181181 RTLIB::SUB_F80,
182182 RTLIB::SUB_PPCF128),
183 NVT, Ops, 2, false/*sign irrelevant*/);
183 NVT, Ops, 2, false);
184184 }
185185
186186 SDOperand DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
546546 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
547547 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
548548
549 case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
549 case ISD::ConstantFP: ExpandFloatRes_ConstantFP(N, Lo, Hi); break;
550 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
551 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
552 case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
553 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
554 case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
555 case ISD::SINT_TO_FP:
556 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
550557 }
551558
552559 // If Lo/Hi is null, the sub-method took care of registering results etc.
553560 if (Lo.Val)
554561 SetExpandedFloat(SDOperand(N, ResNo), Lo, Hi);
562 }
563
564 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo,
565 SDOperand &Hi) {
566 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
567 assert(NVT.getSizeInBits() == integerPartWidth &&
568 "Do not know how to expand this float constant!");
569 APInt C = cast(N)->getValueAPF().convertToAPInt();
570 Lo = DAG.getConstantFP(APFloat(APInt(integerPartWidth, 1,
571 &C.getRawData()[1])), NVT);
572 Hi = DAG.getConstantFP(APFloat(APInt(integerPartWidth, 1,
573 &C.getRawData()[0])), NVT);
574 }
575
576 void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDOperand &Lo,
577 SDOperand &Hi) {
578 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
579 SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
580 RTLIB::ADD_F32,
581 RTLIB::ADD_F64,
582 RTLIB::ADD_F80,
583 RTLIB::ADD_PPCF128),
584 N->getValueType(0), Ops, 2,
585 false);
586 assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
587 Lo = Call.getOperand(0); Hi = Call.getOperand(1);
588 }
589
590 void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDOperand &Lo,
591 SDOperand &Hi) {
592 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
593 SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
594 RTLIB::DIV_F32,
595 RTLIB::DIV_F64,
596 RTLIB::DIV_F80,
597 RTLIB::DIV_PPCF128),
598 N->getValueType(0), Ops, 2,
599 false);
600 assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
601 Lo = Call.getOperand(0); Hi = Call.getOperand(1);
602 }
603
604 void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDOperand &Lo,
605 SDOperand &Hi) {
606 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
607 SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
608 RTLIB::MUL_F32,
609 RTLIB::MUL_F64,
610 RTLIB::MUL_F80,
611 RTLIB::MUL_PPCF128),
612 N->getValueType(0), Ops, 2,
613 false);
614 assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
615 Lo = Call.getOperand(0); Hi = Call.getOperand(1);
616 }
617
618 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDOperand &Lo,
619 SDOperand &Hi) {
620 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
621 SDOperand Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
622 RTLIB::SUB_F32,
623 RTLIB::SUB_F64,
624 RTLIB::SUB_F80,
625 RTLIB::SUB_PPCF128),
626 N->getValueType(0), Ops, 2,
627 false);
628 assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
629 Lo = Call.getOperand(0); Hi = Call.getOperand(1);
555630 }
556631
557632 void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDOperand &Lo,
584659 // Modified the chain - switch anything that used the old chain to use the
585660 // new one.
586661 ReplaceValueWith(SDOperand(LD, 1), Chain);
662 }
663
664 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo,
665 SDOperand &Hi) {
666 assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
667 MVT VT = N->getValueType(0);
668 MVT NVT = TLI.getTypeToTransformTo(VT);
669 SDOperand Src = N->getOperand(0);
670 MVT SrcVT = Src.getValueType();
671
672 // First do an SINT_TO_FP, whether the original was signed or unsigned.
673 if (SrcVT.bitsLE(MVT::i32)) {
674 // The integer can be represented exactly in an f64.
675 Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Src);
676 Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
677 Hi = DAG.getNode(ISD::SINT_TO_FP, NVT, Src);
678 } else {
679 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
680 if (SrcVT.bitsLE(MVT::i64)) {
681 Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Src);
682 LC = RTLIB::SINTTOFP_I64_PPCF128;
683 } else if (SrcVT.bitsLE(MVT::i128)) {
684 Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i128, Src);
685 LC = RTLIB::SINTTOFP_I128_PPCF128;
686 }
687 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
688
689 Hi = MakeLibCall(LC, VT, &Src, 1, true);
690 assert(Hi.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
691 Lo = Hi.getOperand(0); Hi = Hi.getOperand(1);
692 }
693
694 if (N->getOpcode() == ISD::SINT_TO_FP)
695 return;
696
697 // Unsigned - fix up the SINT_TO_FP value just calculated.
698 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
699 SrcVT = Src.getValueType();
700
701 // x>=0 ? (ppcf128)(iN)x : (ppcf128)(iN)x + 2^N; N=32,64,128.
702 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
703 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
704 static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
705 const uint64_t *Parts = 0;
706
707 switch (SrcVT.getSimpleVT()) {
708 default:
709 assert(false && "Unsupported UINT_TO_FP!");
710 case MVT::i32:
711 Parts = TwoE32;
712 case MVT::i64:
713 Parts = TwoE64;
714 case MVT::i128:
715 Parts = TwoE128;
716 }
717
718 Lo = DAG.getNode(ISD::FADD, VT, Hi,
719 DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
720 MVT::ppcf128));
721 Lo = DAG.getNode(ISD::SELECT_CC, VT, Src, DAG.getConstant(0, SrcVT), Lo, Hi,
722 DAG.getCondCode(ISD::SETLT));
723 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Lo,
724 DAG.getConstant(1, TLI.getPointerTy()));
725 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Lo,
726 DAG.getConstant(0, TLI.getPointerTy()));
587727 }
588728
589729
620760 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
621761 case ISD::SELECT_CC: Res = ExpandFloatOp_BR_CC(N); break;
622762 case ISD::SETCC: Res = ExpandFloatOp_BR_CC(N); break;
763
764 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break;
765 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
766 case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
623767
624768 case ISD::STORE:
625769 Res = ExpandFloatOp_STORE(cast(N), OpNo);
727871 DAG.getCondCode(CCCode));
728872 }
729873
874 SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
875 assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
876 "Unsupported FP_TO_UINT!");
877
878 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
879 switch (N->getValueType(0).getSimpleVT()) {
880 default:
881 assert(false && "Unsupported FP_TO_UINT!");
882 case MVT::i32:
883 LC = RTLIB::FPTOUINT_PPCF128_I32;
884 break;
885 case MVT::i64:
886 LC = RTLIB::FPTOUINT_PPCF128_I64;
887 break;
888 case MVT::i128:
889 LC = RTLIB::FPTOUINT_PPCF128_I128;
890 break;
891 }
892
893 return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false);
894 }
895
896 SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
897 assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
898 "Unsupported FP_TO_SINT!");
899
900 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
901 switch (N->getValueType(0).getSimpleVT()) {
902 default:
903 assert(false && "Unsupported FP_TO_SINT!");
904 case MVT::i32:
905 LC = RTLIB::FPTOSINT_PPCF128_I32;
906 case MVT::i64:
907 LC = RTLIB::FPTOSINT_PPCF128_I64;
908 break;
909 case MVT::i128:
910 LC = RTLIB::FPTOSINT_PPCF128_I64;
911 break;
912 }
913
914 return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false);
915 }
916
917 SDOperand DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
918 assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
919 "Logic only correct for ppcf128!");
920 SDOperand Lo, Hi;
921 GetExpandedFloat(N->getOperand(0), Lo, Hi);
922 // Round it the rest of the way (e.g. to f32) if needed.
923 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Hi, N->getOperand(1));
924 }
925
730926 SDOperand DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
731927 if (ISD::isNormalStore(N))
732928 return ExpandOp_NormalStore(N, OpNo);
353353
354354 // Float Result Expansion.
355355 void ExpandFloatResult(SDNode *N, unsigned ResNo);
356 void ExpandFloatRes_LOAD(SDNode *N, SDOperand &Lo, SDOperand &Hi);
356 void ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
357 void ExpandFloatRes_FADD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
358 void ExpandFloatRes_FDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
359 void ExpandFloatRes_FMUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
360 void ExpandFloatRes_FSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
361 void ExpandFloatRes_LOAD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
362 void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
357363
358364 // Float Operand Expansion.
359365 bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
360366 SDOperand ExpandFloatOp_BR_CC(SDNode *N);
367 SDOperand ExpandFloatOp_FP_ROUND(SDNode *N);
368 SDOperand ExpandFloatOp_FP_TO_SINT(SDNode *N);
369 SDOperand ExpandFloatOp_FP_TO_UINT(SDNode *N);
361370 SDOperand ExpandFloatOp_SELECT_CC(SDNode *N);
362371 SDOperand ExpandFloatOp_SETCC(SDNode *N);
363372 SDOperand ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
22432243 break;
22442244 case ISD::EXTRACT_ELEMENT:
22452245 assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!");
2246 assert(!N1.getValueType().isVector() &&
2247 N1.getValueType().isInteger() &&
2248 !VT.isVector() && VT.isInteger() &&
2249 "EXTRACT_ELEMENT only applies to integers!");
2246 assert(!N1.getValueType().isVector() && !VT.isVector() &&
2247 (N1.getValueType().isInteger() == VT.isInteger()) &&
2248 "Wrong types for EXTRACT_ELEMENT!");
22502249
22512250 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
22522251 // 64-bit integers into 32-bit parts. Instead of building the extract of
9696 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
9797 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
9898 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
99 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
99100 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
100101 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
101102 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
107108 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
108109 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
109110 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
111 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
110112 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
111113 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
112114 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";