llvm.org GIT mirror llvm / 0406356
Add Neon VCVT instructions for f32 <-> f16 conversions. Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 9 years ago
7 changed file(s) with 57 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
284284 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
285285 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
286286 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
287
288 // Vector Conversions Between Half-Precision and Single-Precision.
289 def int_arm_neon_vcvtfp2hf
290 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
291 def int_arm_neon_vcvthf2fp
292 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
287293
288294 // Narrowing Saturating Vector Moves.
289295 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
102102 FeatureHasSlowFPVMLx, FeatureT2XtPk]>;
103103 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
104104 "Cortex-A9 ARM processors",
105 [FeatureHasSlowFPVMLx, FeatureT2XtPk]>;
105 [FeatureHasSlowFPVMLx, FeatureT2XtPk,
106 FeatureFP16]>;
106107
107108 class ProcNoItin Features>
108109 : Processor;
155155 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
156156 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
157157 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
158 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
158159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
159160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
160161 AssemblerPredicate;
17221722 : N2V
17231723 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
17241724 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1725
1726 // Long 2-register intrinsics.
1727 class N2VLInt op24_23, bits<2> op21_20, bits<2> op19_18,
1728 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1729 InstrItinClass itin, string OpcodeStr, string Dt,
1730 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1731 : N2V
1732 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1733 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
17251734
17261735 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
17271736 class N2VDShuffle op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
44464455 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
44474456 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
44484457
4458 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4459 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4460 IIC_VUNAQ, "vcvt", "f16.f32",
4461 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4462 Requires<[HasNEON, HasFP16]>;
4463 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4464 IIC_VUNAQ, "vcvt", "f32.f16",
4465 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4466 Requires<[HasNEON, HasFP16]>;
4467
44494468 // Vector Reverse.
44504469
44514470 // VREV64 : Vector Reverse elements within 64-bit doublewords
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
11
22 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
33 ;CHECK: vcvt_f32tos32:
137137 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
138138 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
139139
140 define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
141 ;CHECK: vcvt_f16tof32:
142 ;CHECK: vcvt.f32.f16
143 %tmp1 = load <4 x i16>* %A
144 %tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
145 ret <4 x float> %tmp2
146 }
147
148 define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
149 ;CHECK: vcvt_f32tof16:
150 ;CHECK: vcvt.f16.f32
151 %tmp1 = load <4 x float>* %A
152 %tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
153 ret <4 x i16> %tmp2
154 }
155
156 declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
157 declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
None @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
0 @ RUN: llvm-mc -mcpu=cortex-a9 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
11
22 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
33 vcvt.s32.f32 d16, d16
3131 vcvt.f32.s32 q8, q8, #1
3232 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
3333 vcvt.f32.u32 q8, q8, #1
34 @ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0x20,0x07,0xf6,0xf3]
35 vcvt.f32.f16 q8, d16
36 @ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0x20,0x06,0xf6,0xf3]
37 vcvt.f16.f32 d16, q8
None @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
0 @ RUN: llvm-mc -mcpu=cortex-a9 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
11
22 .code 16
33
3333 vcvt.f32.s32 q8, q8, #1
3434 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
3535 vcvt.f32.u32 q8, q8, #1
36 @ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0xf6,0xff,0x20,0x07]
37 vcvt.f32.f16 q8, d16
38 @ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x06]
39 vcvt.f16.f32 d16, q8