llvm.org GIT mirror llvm / 03cd663
R600/SI: Move splitting 64-bit immediates to separate function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204651 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 6 years ago
2 changed file(s) with 60 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
590590 return SubReg;
591591 }
592592
593 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl &Worklist,
594 MachineBasicBlock::iterator MI,
595 MachineRegisterInfo &MRI,
596 const TargetRegisterClass *RC,
597 const MachineOperand &Op) const {
598 MachineBasicBlock *MBB = MI->getParent();
599 DebugLoc DL = MI->getDebugLoc();
600 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
601 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
602 unsigned Dst = MRI.createVirtualRegister(RC);
603
604 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
605 LoDst)
606 .addImm(Op.getImm() & 0xFFFFFFFF);
607 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
608 HiDst)
609 .addImm(Op.getImm() >> 32);
610
611 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
612 .addReg(LoDst)
613 .addImm(AMDGPU::sub0)
614 .addReg(HiDst)
615 .addImm(AMDGPU::sub1);
616
617 Worklist.push_back(Lo);
618 Worklist.push_back(Hi);
619
620 return Dst;
621 }
622
593623 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
594624 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
595625 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
824854
825855 // Handle some special cases
826856 switch(Inst->getOpcode()) {
827 case AMDGPU::S_MOV_B64: {
828 DebugLoc DL = Inst->getDebugLoc();
829
830 // If the source operand is a register we can replace this with a
831 // copy
832 if (Inst->getOperand(1).isReg()) {
833 MachineInstr *Copy = BuildMI(*MBB, Inst, DL,
834 get(TargetOpcode::COPY))
835 .addOperand(Inst->getOperand(0))
836 .addOperand(Inst->getOperand(1));
837 Worklist.push_back(Copy);
838 } else {
839 // Otherwise, we need to split this into two movs, because there is
840 // no 64-bit VALU move instruction.
841 unsigned LoDst, HiDst, Dst;
842 LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
843 HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
844 Dst = MRI.createVirtualRegister(
845 MRI.getRegClass(Inst->getOperand(0).getReg()));
846
847 MachineInstr *Lo = BuildMI(*MBB, Inst, DL, get(AMDGPU::S_MOV_B32),
848 LoDst)
849 .addImm(Inst->getOperand(1).getImm() & 0xFFFFFFFF);
850 MachineInstr *Hi = BuildMI(*MBB, Inst, DL, get(AMDGPU::S_MOV_B32),
851 HiDst)
852 .addImm(Inst->getOperand(1).getImm() >> 32);
853
854 BuildMI(*MBB, Inst, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
855 .addReg(LoDst)
856 .addImm(AMDGPU::sub0)
857 .addReg(HiDst)
858 .addImm(AMDGPU::sub1);
859
860 MRI.replaceRegWith(Inst->getOperand(0).getReg(), Dst);
861 Worklist.push_back(Lo);
862 Worklist.push_back(Hi);
863 }
864 Inst->eraseFromParent();
865 continue;
866 }
857 case AMDGPU::S_MOV_B64: {
858 DebugLoc DL = Inst->getDebugLoc();
859
860 // If the source operand is a register we can replace this with a
861 // copy.
862 if (Inst->getOperand(1).isReg()) {
863 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
864 .addOperand(Inst->getOperand(0))
865 .addOperand(Inst->getOperand(1));
866 Worklist.push_back(Copy);
867 } else {
868 // Otherwise, we need to split this into two movs, because there is
869 // no 64-bit VALU move instruction.
870 unsigned Reg = Inst->getOperand(0).getReg();
871 unsigned Dst = split64BitImm(Worklist,
872 Inst,
873 MRI,
874 MRI.getRegClass(Reg),
875 Inst->getOperand(1));
876 MRI.replaceRegWith(Reg, Dst);
877 }
878 Inst->eraseFromParent();
879 continue;
880 }
867881 }
868882
869883 unsigned NewOpcode = getVALUOp(*Inst);
3030 const TargetRegisterClass *SuperRC,
3131 unsigned SubIdx,
3232 const TargetRegisterClass *SubRC) const;
33
34 unsigned split64BitImm(SmallVectorImpl &Worklist,
35 MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 const TargetRegisterClass *RC,
38 const MachineOperand &Op) const;
3339
3440 public:
3541 explicit SIInstrInfo(AMDGPUTargetMachine &tm);