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Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
2 changed file(s) with 15 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
61416141
61426142 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
61436143 /// uses N as its base pointer and that N may be folded in the load / store
6144 /// addressing mode. FIXME: This currently only looks for folding of
6145 /// [reg +/- imm] addressing modes.
6144 /// addressing mode.
61466145 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
61476146 SelectionDAG &DAG,
61486147 const TargetLowering &TLI) {
61626161 if (N->getOpcode() == ISD::ADD) {
61636162 ConstantSDNode *Offset = dyn_cast(N->getOperand(1));
61646163 if (Offset)
6164 // [reg +/- imm]
61656165 AM.BaseOffs = Offset->getSExtValue();
61666166 else
6167 return false;
6167 // [reg +/- reg]
6168 AM.Scale = 1;
61686169 } else if (N->getOpcode() == ISD::SUB) {
61696170 ConstantSDNode *Offset = dyn_cast(N->getOperand(1));
61706171 if (Offset)
6172 // [reg +/- imm]
61716173 AM.BaseOffs = -Offset->getSExtValue();
61726174 else
6173 return false;
6175 // [reg +/- reg]
6176 AM.Scale = 1;
61746177 } else
61756178 return false;
61766179
5353 define fastcc void @test4(i16 %addr) nounwind {
5454 entry:
5555 ; A8: test4:
56 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
57 ; A8: str [[REG]], [r0]
56 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
57 ; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
58 ; A8: str [[REG]], [r0, r1, lsl #2]
59 ; A8-NOT: str [[REG]], [r0]
5860
5961 ; A9: test4:
60 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
61 ; A9: str [[REG]], [r0]
62 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
63 ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
64 ; A9: str [[REG]], [r0, r1, lsl #2]
65 ; A9-NOT: str [[REG]], [r0]
6266 %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
6367 %1 = bitcast i8* %0 to i32*
6468 %2 = sext i16 %addr to i32