llvm.org GIT mirror llvm / 036c045
Switch from EVT to MVT in more of the x86 instruction lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198144 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
1 changed file(s) with 44 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
85058505 /// and take a 2 x i32 value to shift plus a shift amount.
85068506 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
85078507 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8508 EVT VT = Op.getValueType();
8508 MVT VT = Op.getSimpleValueType();
85098509 unsigned VTBits = VT.getSizeInBits();
85108510 SDLoc dl(Op);
85118511 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
85578557
85588558 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
85598559 SelectionDAG &DAG) const {
8560 EVT SrcVT = Op.getOperand(0).getValueType();
8560 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
85618561
85628562 if (SrcVT.isVector())
85638563 return SDValue();
85648564
8565 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8565 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
85668566 "Unknown SINT_TO_FP to lower!");
85678567
85688568 // These are really Legal; return the operand so the caller accepts it as
87668766 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
87678767 SelectionDAG &DAG) const {
87688768 SDValue N0 = Op.getOperand(0);
8769 EVT SVT = N0.getValueType();
8769 MVT SVT = N0.getSimpleValueType();
87708770 SDLoc dl(Op);
87718771
87728772 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
87738773 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
87748774 "Custom UINT_TO_FP is not supported!");
87758775
8776 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8777 SVT.getVectorNumElements());
8776 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
87788777 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
87798778 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
87808779 }
87938792 if (DAG.SignBitIsZero(N0))
87948793 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
87958794
8796 EVT SrcVT = N0.getValueType();
8797 EVT DstVT = Op.getValueType();
8795 MVT SrcVT = N0.getSimpleValueType();
8796 MVT DstVT = Op.getSimpleValueType();
87988797 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
87998798 return LowerUINT_TO_FP_i64(Op, DAG);
88008799 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
90089007
90099008 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
90109009 SelectionDAG &DAG) {
9011 MVT VT = Op->getValueType(0).getSimpleVT();
9010 MVT VT = Op->getSimpleValueType(0);
90129011 SDValue In = Op->getOperand(0);
9013 MVT InVT = In.getValueType().getSimpleVT();
9012 MVT InVT = In.getSimpleValueType();
90149013 SDLoc DL(Op);
90159014 unsigned int NumElts = VT.getVectorNumElements();
90169015 if (NumElts != 8 && NumElts != 16)
92089207 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
92099208
92109209 unsigned NumElems = VT.getVectorNumElements();
9211 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9212 NumElems * 2);
9210 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
92139211
92149212 SmallVector MaskVec(NumElems * 2, -1);
92159213 // Prepare truncation shuffle mask
1109911097
1110011098 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
1110111099 // amount is a constant. Takes immediate version of shift as input.
11102 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
11100 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
1110311101 SDValue SrcOp, uint64_t ShiftAmt,
1110411102 SelectionDAG &DAG) {
11105 EVT ElementType = VT.getVectorElementType();
11103 MVT ElementType = VT.getVectorElementType();
1110611104
1110711105 // Check for ShiftAmt >= element width
1110811106 if (ShiftAmt >= ElementType.getSizeInBits()) {
1117011168
1117111169 // getTargetVShiftNode - Handle vector element shifts where the shift amount
1117211170 // may or may not be a constant. Takes immediate version of shift as input.
11173 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
11171 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
1117411172 SDValue SrcOp, SDValue ShAmt,
1117511173 SelectionDAG &DAG) {
1117611174 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
1119811196
1119911197 // The return type has to be a 128-bit type with the same element
1120011198 // type as the input type.
11201 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11199 MVT EltVT = VT.getVectorElementType();
1120211200 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
1120311201
1120411202 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
1173111729 Opcode = X86ISD::VSRAI;
1173211730 break;
1173311731 }
11734 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11732 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
1173511733 Op.getOperand(1), Op.getOperand(2), DAG);
1173611734 }
1173711735
1244812446 const TargetMachine &TM = MF.getTarget();
1244912447 const TargetFrameLowering &TFI = *TM.getFrameLowering();
1245012448 unsigned StackAlignment = TFI.getStackAlignment();
12451 EVT VT = Op.getValueType();
12449 MVT VT = Op.getSimpleValueType();
1245212450 SDLoc DL(Op);
1245312451
1245412452 // Save FP Control Word to stack slot
1249312491 }
1249412492
1249512493 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12496 EVT VT = Op.getValueType();
12494 MVT VT = Op.getSimpleValueType();
1249712495 EVT OpVT = VT;
1249812496 unsigned NumBits = VT.getSizeInBits();
1249912497 SDLoc dl(Op);
1252712525 }
1252812526
1252912527 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12530 EVT VT = Op.getValueType();
12528 MVT VT = Op.getSimpleValueType();
1253112529 EVT OpVT = VT;
1253212530 unsigned NumBits = VT.getSizeInBits();
1253312531 SDLoc dl(Op);
1255212550 }
1255312551
1255412552 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12555 EVT VT = Op.getValueType();
12553 MVT VT = Op.getSimpleValueType();
1255612554 unsigned NumBits = VT.getSizeInBits();
1255712555 SDLoc dl(Op);
1255812556 Op = Op.getOperand(0);
1257412572 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
1257512573 // ones, and then concatenate the result back.
1257612574 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12577 EVT VT = Op.getValueType();
12575 MVT VT = Op.getSimpleValueType();
1257812576
1257912577 assert(VT.is256BitVector() && VT.isInteger() &&
1258012578 "Unsupported value type for operation");
1259212590 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
1259312591 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
1259412592
12595 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12596 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12593 MVT EltVT = VT.getVectorElementType();
12594 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
1259712595
1259812596 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
1259912597 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
1260112599 }
1260212600
1260312601 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12604 assert(Op.getValueType().is256BitVector() &&
12605 Op.getValueType().isInteger() &&
12602 assert(Op.getSimpleValueType().is256BitVector() &&
12603 Op.getSimpleValueType().isInteger() &&
1260612604 "Only handle AVX 256-bit vector integer operation");
1260712605 return Lower256IntArith(Op, DAG);
1260812606 }
1260912607
1261012608 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12611 assert(Op.getValueType().is256BitVector() &&
12612 Op.getValueType().isInteger() &&
12609 assert(Op.getSimpleValueType().is256BitVector() &&
12610 Op.getSimpleValueType().isInteger() &&
1261312611 "Only handle AVX 256-bit vector integer operation");
1261412612 return Lower256IntArith(Op, DAG);
1261512613 }
1261712615 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
1261812616 SelectionDAG &DAG) {
1261912617 SDLoc dl(Op);
12620 EVT VT = Op.getValueType();
12618 MVT VT = Op.getSimpleValueType();
1262112619
1262212620 // Decompose 256-bit ops into smaller 128-bit ops.
1262312621 if (VT.is256BitVector() && !Subtarget->hasInt256())
1268712685 }
1268812686
1268912687 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12690 EVT VT = Op.getValueType();
12691 EVT EltTy = VT.getVectorElementType();
12688 MVT VT = Op.getSimpleValueType();
12689 MVT EltTy = VT.getVectorElementType();
1269212690 unsigned NumElts = VT.getVectorNumElements();
1269312691 SDValue N0 = Op.getOperand(0);
1269412692 SDLoc dl(Op);
1274312741
1274412742 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
1274512743 const X86Subtarget *Subtarget) {
12746 EVT VT = Op.getValueType();
12744 MVT VT = Op.getSimpleValueType();
1274712745 SDLoc dl(Op);
1274812746 SDValue R = Op.getOperand(0);
1274912747 SDValue Amt = Op.getOperand(1);
1287012868 Amt.getOpcode() == ISD::BITCAST &&
1287112869 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1287212870 Amt = Amt.getOperand(0);
12873 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12871 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
1287412872 VT.getVectorNumElements();
1287512873 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
1287612874 uint64_t ShiftAmt = 0;
1291512913
1291612914 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
1291712915 const X86Subtarget* Subtarget) {
12918 EVT VT = Op.getValueType();
12916 MVT VT = Op.getSimpleValueType();
1291912917 SDLoc dl(Op);
1292012918 SDValue R = Op.getOperand(0);
1292112919 SDValue Amt = Op.getOperand(1);
1298512983 default:
1298612984 llvm_unreachable("Unknown shift opcode!");
1298712985 case ISD::SHL:
12988 switch (VT.getSimpleVT().SimpleTy) {
12986 switch (VT.SimpleTy) {
1298912987 default: return SDValue();
1299012988 case MVT::v2i64:
1299112989 case MVT::v4i32:
1299812996 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
1299912997 }
1300012998 case ISD::SRA:
13001 switch (VT.getSimpleVT().SimpleTy) {
12999 switch (VT.SimpleTy) {
1300213000 default: return SDValue();
1300313001 case MVT::v4i32:
1300413002 case MVT::v8i16:
1300913007 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
1301013008 }
1301113009 case ISD::SRL:
13012 switch (VT.getSimpleVT().SimpleTy) {
13010 switch (VT.SimpleTy) {
1301313011 default: return SDValue();
1301413012 case MVT::v2i64:
1301513013 case MVT::v4i32:
1303213030 Amt.getOpcode() == ISD::BITCAST &&
1303313031 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1303413032 Amt = Amt.getOperand(0);
13035 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
13033 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
1303613034 VT.getVectorNumElements();
1303713035 std::vector Vals(Ratio);
1303813036 for (unsigned i = 0; i != Ratio; ++i)
1306013058 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
1306113059 SelectionDAG &DAG) {
1306213060
13063 EVT VT = Op.getValueType();
13061 MVT VT = Op.getSimpleValueType();
1306413062 SDLoc dl(Op);
1306513063 SDValue R = Op.getOperand(0);
1306613064 SDValue Amt = Op.getOperand(1);
1314813146 // Decompose 256-bit shifts into smaller 128-bit shifts.
1314913147 if (VT.is256BitVector()) {
1315013148 unsigned NumElems = VT.getVectorNumElements();
13151 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13149 MVT EltVT = VT.getVectorElementType();
1315213150 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
1315313151
1315413152 // Extract the two vectors
1326613264 SelectionDAG &DAG) const {
1326713265 SDLoc dl(Op);
1326813266 EVT ExtraVT = cast(Op.getOperand(1))->getVT();
13269 EVT VT = Op.getValueType();
13267 MVT VT = Op.getSimpleValueType();
1327013268
1327113269 if (!Subtarget->hasSSE2() || !VT.isVector())
1327213270 return SDValue();
1327413272 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
1327513273 ExtraVT.getScalarType().getSizeInBits();
1327613274
13277 switch (VT.getSimpleVT().SimpleTy) {
13275 switch (VT.SimpleTy) {
1327813276 default: return SDValue();
1327913277 case MVT::v8i32:
1328013278 case MVT::v16i16:
1328913287 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
1329013288 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
1329113289
13292 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13290 MVT EltVT = VT.getVectorElementType();
1329313291 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
1329413292
1329513293 EVT ExtraEltVT = ExtraVT.getVectorElementType();
1337613374
1337713375 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
1337813376 SelectionDAG &DAG) {
13379 EVT T = Op.getValueType();
13377 MVT T = Op.getSimpleValueType();
1338013378 SDLoc DL(Op);
1338113379 unsigned Reg = 0;
1338213380 unsigned size = 0;
13383 switch(T.getSimpleVT().SimpleTy) {
13381 switch(T.SimpleTy) {
1338413382 default: llvm_unreachable("Invalid value type!");
1338513383 case MVT::i8: Reg = X86::AL; size = 1; break;
1338613384 case MVT::i16: Reg = X86::AX; size = 2; break;
1348813486 }
1348913487
1349013488 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13491 EVT VT = Op.getNode()->getValueType(0);
13489 EVT VT = Op.getNode()->getSimpleValueType(0);
1349213490
1349313491 // Let legalize expand this if it isn't a legal type yet.
1349413492 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))