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Strip trailing whitespace. NFCI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308143 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
1 changed file(s) with 65 addition(s) and 65 deletion(s). Raw diff Collapse all Expand all
17581758 (i64 0)),
17591759 (COPY_TO_REGCLASS (!cast(InstrStr##rr) _.RC:$src1, _.RC:$src2),
17601760 NewInf.KRC)>;
1761
1761
17621762 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
1763 (_.KVT (OpNode (_.VT _.RC:$src1),
1763 (_.KVT (OpNode (_.VT _.RC:$src1),
17641764 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
17651765 (i64 0)),
17661766 (COPY_TO_REGCLASS (!cast(InstrStr##rm) _.RC:$src1, addr:$src2),
17671767 NewInf.KRC)>;
1768
1768
17691769 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
1770 (_.KVT (and _.KRCWM:$mask,
1770 (_.KVT (and _.KRCWM:$mask,
17711771 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))),
17721772 (i64 0)),
17731773 (COPY_TO_REGCLASS (!cast(InstrStr##rrk) _.KRCWM:$mask,
17741774 _.RC:$src1, _.RC:$src2),
17751775 NewInf.KRC)>;
1776
1776
17771777 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
1778 (_.KVT (and (_.KVT _.KRCWM:$mask),
1779 (_.KVT (OpNode (_.VT _.RC:$src1),
1780 (_.VT (bitconvert
1778 (_.KVT (and (_.KVT _.KRCWM:$mask),
1779 (_.KVT (OpNode (_.VT _.RC:$src1),
1780 (_.VT (bitconvert
17811781 (_.LdFrag addr:$src2))))))),
17821782 (i64 0)),
1783 (COPY_TO_REGCLASS (!cast(InstrStr##rmk) _.KRCWM:$mask,
1783 (COPY_TO_REGCLASS (!cast(InstrStr##rmk) _.KRCWM:$mask,
17841784 _.RC:$src1, addr:$src2),
17851785 NewInf.KRC)>;
17861786 }
17971797 (i64 0)),
17981798 (COPY_TO_REGCLASS (!cast(InstrStr##rmb) _.RC:$src1, addr:$src2),
17991799 NewInf.KRC)>;
1800
1800
18011801 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
18021802 (_.KVT (and (_.KVT _.KRCWM:$mask),
18031803 (_.KVT (OpNode (_.VT _.RC:$src1),
18781878 defm : avx512_icmp_packed_rmb_lowering
18791879 "VPCMPEQQZ256", [HasAVX512, HasVLX]>;
18801880
1881 defm : avx512_icmp_packed_rmb_lowering
1881 defm : avx512_icmp_packed_rmb_lowering
18821882 "VPCMPEQQZ", [HasAVX512]>;
18831883 defm : avx512_icmp_packed_rmb_lowering
18841884 "VPCMPEQQZ", [HasAVX512]>;
21262126 list Preds> {
21272127 let Predicates = Preds in {
21282128 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2129 (_.KVT (OpNode (_.VT _.RC:$src1),
2130 (_.VT _.RC:$src2),
2129 (_.KVT (OpNode (_.VT _.RC:$src1),
2130 (_.VT _.RC:$src2),
21312131 imm:$cc)),
21322132 (i64 0)),
2133 (COPY_TO_REGCLASS (!cast(InstrStr##rri) _.RC:$src1,
2133 (COPY_TO_REGCLASS (!cast(InstrStr##rri) _.RC:$src1,
21342134 _.RC:$src2,
21352135 imm:$cc),
21362136 NewInf.KRC)>;
2137
2137
21382138 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2139 (_.KVT (OpNode (_.VT _.RC:$src1),
2139 (_.KVT (OpNode (_.VT _.RC:$src1),
21402140 (_.VT (bitconvert (_.LdFrag addr:$src2))),
21412141 imm:$cc)),
21422142 (i64 0)),
21442144 addr:$src2,
21452145 imm:$cc),
21462146 NewInf.KRC)>;
2147
2147
21482148 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2149 (_.KVT (and _.KRCWM:$mask,
2149 (_.KVT (and _.KRCWM:$mask,
21502150 (OpNode (_.VT _.RC:$src1),
21512151 (_.VT _.RC:$src2),
21522152 imm:$cc))),
21532153 (i64 0)),
21542154 (COPY_TO_REGCLASS (!cast(InstrStr##rrik) _.KRCWM:$mask,
2155 _.RC:$src1,
2155 _.RC:$src1,
21562156 _.RC:$src2,
21572157 imm:$cc),
21582158 NewInf.KRC)>;
2159
2159
21602160 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2161 (_.KVT (and (_.KVT _.KRCWM:$mask),
2162 (_.KVT (OpNode (_.VT _.RC:$src1),
2163 (_.VT (bitconvert
2161 (_.KVT (and (_.KVT _.KRCWM:$mask),
2162 (_.KVT (OpNode (_.VT _.RC:$src1),
2163 (_.VT (bitconvert
21642164 (_.LdFrag addr:$src2))),
21652165 imm:$cc)))),
21662166 (i64 0)),
2167 (COPY_TO_REGCLASS (!cast(InstrStr##rmik) _.KRCWM:$mask,
2167 (COPY_TO_REGCLASS (!cast(InstrStr##rmik) _.KRCWM:$mask,
21682168 _.RC:$src1,
21692169 addr:$src2,
21702170 imm:$cc),
21712171 NewInf.KRC)>;
21722172 }
21732173 }
2174
2174
21752175 multiclass avx512_icmp_cc_packed_rmb_lowering
21762176 SDNode OpNode, string InstrStr,
2177 list Preds>
2177 list Preds>
21782178 : avx512_icmp_cc_packed_lowering<_, NewInf, OpNode, InstrStr, Preds> {
21792179 let Predicates = Preds in {
21802180 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
21862186 addr:$src2,
21872187 imm:$cc),
21882188 NewInf.KRC)>;
2189
2189
21902190 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
21912191 (_.KVT (and (_.KVT _.KRCWM:$mask),
21922192 (_.KVT (OpNode (_.VT _.RC:$src1),
24462446 string InstrStr, list Preds> {
24472447 let Predicates = Preds in {
24482448 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2449 (_.KVT (X86cmpm (_.VT _.RC:$src1),
2450 (_.VT _.RC:$src2),
2449 (_.KVT (X86cmpm (_.VT _.RC:$src1),
2450 (_.VT _.RC:$src2),
24512451 imm:$cc)),
24522452 (i64 0)),
2453 (COPY_TO_REGCLASS (!cast(InstrStr##rri) _.RC:$src1,
2453 (COPY_TO_REGCLASS (!cast(InstrStr##rri) _.RC:$src1,
24542454 _.RC:$src2,
24552455 imm:$cc),
24562456 NewInf.KRC)>;
2457
2457
24582458 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2459 (_.KVT (X86cmpm (_.VT _.RC:$src1),
2459 (_.KVT (X86cmpm (_.VT _.RC:$src1),
24602460 (_.VT (bitconvert (_.LdFrag addr:$src2))),
24612461 imm:$cc)),
24622462 (i64 0)),
24762476 NewInf.KRC)>;
24772477 }
24782478 }
2479
2479
24802480 multiclass avx512_fcmp_cc_packed_sae_lowering
2481 string InstrStr, list Preds>
2481 string InstrStr, list Preds>
24822482 : avx512_fcmp_cc_packed_lowering<_, NewInf, InstrStr, Preds> {
24832483
24842484 let Predicates = Preds in
24852485 def : Pat<(insert_subvector (NewInf.KVT immAllZerosV),
2486 (_.KVT (X86cmpmRnd (_.VT _.RC:$src1),
2487 (_.VT _.RC:$src2),
2486 (_.KVT (X86cmpmRnd (_.VT _.RC:$src1),
2487 (_.VT _.RC:$src2),
24882488 imm:$cc,
24892489 (i32 FROUND_NO_EXC))),
24902490 (i64 0)),
2491 (COPY_TO_REGCLASS (!cast(InstrStr##rrib) _.RC:$src1,
2491 (COPY_TO_REGCLASS (!cast(InstrStr##rrib) _.RC:$src1,
24922492 _.RC:$src2,
24932493 imm:$cc),
24942494 NewInf.KRC)>;
28162816 def : Pat<(maskVT (scalar_to_vector GR32:$src)),
28172817 (COPY_TO_REGCLASS GR32:$src, maskRC)>;
28182818
2819 def : Pat<(i32 (X86Vextract maskRC:$src, (iPTR 0))),
2819 def : Pat<(i32 (X86Vextract maskRC:$src, (iPTR 0))),
28202820 (COPY_TO_REGCLASS maskRC:$src, GR32)>;
28212821
28222822 def : Pat<(maskVT (scalar_to_vector GR8:$src)),
28232823 (COPY_TO_REGCLASS (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), maskRC)>;
28242824
2825 def : Pat<(i8 (X86Vextract maskRC:$src, (iPTR 0))),
2825 def : Pat<(i8 (X86Vextract maskRC:$src, (iPTR 0))),
28262826 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS maskRC:$src, GR32)), sub_8bit)>;
28272827
2828 def : Pat<(i32 (anyext (i8 (X86Vextract maskRC:$src, (iPTR 0))))),
2828 def : Pat<(i32 (anyext (i8 (X86Vextract maskRC:$src, (iPTR 0))))),
28292829 (COPY_TO_REGCLASS maskRC:$src, GR32)>;
28302830 }
28312831
30353035 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
30363036 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm))), VK8)>;
30373037
3038 def : Pat<(insert_subvector (v16i1 immAllZerosV),
3038 def : Pat<(insert_subvector (v16i1 immAllZerosV),
30393039 (v8i1 (OpNode (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
30403040 (i64 0)),
30413041 (KSHIFTRWri (KSHIFTLWri (!cast(InstStr##Zrr)
30433043 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm))),
30443044 (i8 8)), (i8 8))>;
30453045
3046 def : Pat<(insert_subvector (v16i1 immAllZerosV),
3047 (v8i1 (and VK8:$mask,
3046 def : Pat<(insert_subvector (v16i1 immAllZerosV),
3047 (v8i1 (and VK8:$mask,
30483048 (OpNode (v8i32 VR256X:$src1), (v8i32 VR256X:$src2)))),
30493049 (i64 0)),
30503050 (KSHIFTRWri (KSHIFTLWri (!cast(InstStr##Zrrk)
30623062 (_.info512.VT (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)),
30633063 imm:$cc), VK8)>;
30643064
3065 def : Pat<(insert_subvector (v16i1 immAllZerosV),
3065 def : Pat<(insert_subvector (v16i1 immAllZerosV),
30663066 (v8i1 (OpNode (_.info256.VT VR256X:$src1), (_.info256.VT VR256X:$src2), imm:$cc)),
30673067 (i64 0)),
30683068 (KSHIFTRWri (KSHIFTLWri (!cast(InstStr##Zrri)
30713071 imm:$cc),
30723072 (i8 8)), (i8 8))>;
30733073
3074 def : Pat<(insert_subvector (v16i1 immAllZerosV),
3075 (v8i1 (and VK8:$mask,
3074 def : Pat<(insert_subvector (v16i1 immAllZerosV),
3075 (v8i1 (and VK8:$mask,
30763076 (OpNode (_.info256.VT VR256X:$src1), (_.info256.VT VR256X:$src2), imm:$cc))),
30773077 (i64 0)),
30783078 (KSHIFTRWri (KSHIFTLWri (!cast(InstStr##Zrrik)
33783378 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
33793379 HasAVX512>,
33803380 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
3381 HasAVX512, "VMOVDQA32">,
3381 HasAVX512, "VMOVDQA32">,
33823382 PD, EVEX_CD8<32, CD8VF>;
33833383
33843384 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
33853385 HasAVX512>,
33863386 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
3387 HasAVX512, "VMOVDQA64">,
3387 HasAVX512, "VMOVDQA64">,
33883388 PD, VEX_W, EVEX_CD8<64, CD8VF>;
33893389
33903390 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
33913391 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
3392 HasBWI, "VMOVDQU8">,
3392 HasBWI, "VMOVDQU8">,
33933393 XD, EVEX_CD8<8, CD8VF>;
33943394
33953395 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
33963396 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
3397 HasBWI, "VMOVDQU16">,
3397 HasBWI, "VMOVDQU16">,
33983398 XD, VEX_W, EVEX_CD8<16, CD8VF>;
33993399
34003400 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512,
34013401 null_frag>,
34023402 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
3403 HasAVX512, "VMOVDQU32">,
3403 HasAVX512, "VMOVDQU32">,
34043404 XS, EVEX_CD8<32, CD8VF>;
34053405
34063406 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512,
34073407 null_frag>,
34083408 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
3409 HasAVX512, "VMOVDQU64">,
3409 HasAVX512, "VMOVDQU64">,
34103410 XS, VEX_W, EVEX_CD8<64, CD8VF>;
34113411
34123412 // Special instructions to help with spilling when we don't have VLX. We need
39633963 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
39643964
39653965 let hasSideEffects = 0 in {
3966 def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3966 def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
39673967 (ins VR128X:$src1, FR32X:$src2),
39683968 "vmovss.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
39693969 [], NoItinerary>, XS, EVEX_4V, VEX_LIG,
39703970 FoldGenData<"VMOVSSZrr">;
39713971
39723972 let Constraints = "$src0 = $dst" in
3973 def VMOVSSZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3974 (ins f32x_info.RC:$src0, f32x_info.KRCWM:$mask,
3973 def VMOVSSZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3974 (ins f32x_info.RC:$src0, f32x_info.KRCWM:$mask,
39753975 VR128X:$src1, FR32X:$src2),
39763976 "vmovss.s\t{$src2, $src1, $dst {${mask}}|"#
39773977 "$dst {${mask}}, $src1, $src2}",
39783978 [], NoItinerary>, EVEX_K, XS, EVEX_4V, VEX_LIG,
39793979 FoldGenData<"VMOVSSZrrk">;
3980
3981 def VMOVSSZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3980
3981 def VMOVSSZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
39823982 (ins f32x_info.KRCWM:$mask, VR128X:$src1, FR32X:$src2),
39833983 "vmovss.s\t{$src2, $src1, $dst {${mask}} {z}|"#
39843984 "$dst {${mask}} {z}, $src1, $src2}",
39853985 [], NoItinerary>, EVEX_KZ, XS, EVEX_4V, VEX_LIG,
39863986 FoldGenData<"VMOVSSZrrkz">;
39873987
3988 def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3988 def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
39893989 (ins VR128X:$src1, FR64X:$src2),
39903990 "vmovsd.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
39913991 [], NoItinerary>, XD, EVEX_4V, VEX_LIG, VEX_W,
39923992 FoldGenData<"VMOVSDZrr">;
39933993
39943994 let Constraints = "$src0 = $dst" in
3995 def VMOVSDZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3996 (ins f64x_info.RC:$src0, f64x_info.KRCWM:$mask,
3995 def VMOVSDZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
3996 (ins f64x_info.RC:$src0, f64x_info.KRCWM:$mask,
39973997 VR128X:$src1, FR64X:$src2),
39983998 "vmovsd.s\t{$src2, $src1, $dst {${mask}}|"#
39993999 "$dst {${mask}}, $src1, $src2}",
40004000 [], NoItinerary>, EVEX_K, XD, EVEX_4V, VEX_LIG,
4001 VEX_W, FoldGenData<"VMOVSDZrrk">;
4002
4003 def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
4004 (ins f64x_info.KRCWM:$mask, VR128X:$src1,
4001 VEX_W, FoldGenData<"VMOVSDZrrk">;
4002
4003 def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
4004 (ins f64x_info.KRCWM:$mask, VR128X:$src1,
40054005 FR64X:$src2),
40064006 "vmovsd.s\t{$src2, $src1, $dst {${mask}} {z}|"#
40074007 "$dst {${mask}} {z}, $src1, $src2}",
4008 [], NoItinerary>, EVEX_KZ, XD, EVEX_4V, VEX_LIG,
4008 [], NoItinerary>, EVEX_KZ, XD, EVEX_4V, VEX_LIG,
40094009 VEX_W, FoldGenData<"VMOVSDZrrkz">;
40104010 }
40114011