llvm.org GIT mirror llvm / 027113d
Complete the missing parts of MIPS-JIT functionality. Patch by Petar Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143014 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
8 changed file(s) with 207 addition(s) and 125 deletion(s). Raw diff Collapse all Expand all
11
22 llvm_tablegen(MipsGenRegisterInfo.inc -gen-register-info)
33 llvm_tablegen(MipsGenInstrInfo.inc -gen-instr-info)
4 llvm_tablegen(MipsGenCodeEmitter.inc -gen-emitter)
45 llvm_tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
56 llvm_tablegen(MipsGenDAGISel.inc -gen-dag-isel)
67 llvm_tablegen(MipsGenCallingConv.inc -gen-callingconv)
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
15 MipsGenAsmWriter.inc \
15 MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
1616 MipsGenDAGISel.inc MipsGenCallingConv.inc \
1717 MipsGenSubtargetInfo.inc
1818
3838 // Shifts
3939 class LogicR_shift_rotate_imm64 func, bits<5> _rs, string instr_asm,
4040 SDNode OpNode, PatFrag PF>:
41 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, shamt_64:$c),
42 !strconcat(instr_asm, "\t$dst, $b, $c"),
43 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, (i64 PF:$c)))],
41 FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt, shamt_64:$shamt),
42 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
43 [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, (i64 PF:$shamt)))],
4444 IIAlu> {
4545 let rs = _rs;
4646 }
4747
4848 class LogicR_shift_rotate_reg64 func, bits<5> _shamt, string instr_asm,
4949 SDNode OpNode>:
50 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
51 !strconcat(instr_asm, "\t$dst, $b, $c"),
52 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
50 FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs, CPU64Regs:$rt),
51 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
52 [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, CPU64Regs:$rs))], IIAlu> {
5353 let shamt = _shamt;
5454 }
5555
5656 // Mul, Div
57 let Defs = [HI64, LO64] in {
57 let rd = 0, shamt = 0, Defs = [HI64, LO64] in {
5858 let isCommutable = 1 in
5959 class Mul64 func, string instr_asm, InstrItinClass itin>:
60 FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
61 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
60 FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt),
61 !strconcat(instr_asm, "\t$rs, $rt"), [], itin>;
6262
6363 class Div64 func, string instr_asm, InstrItinClass itin>:
64 FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
65 !strconcat(instr_asm, "\t$$zero, $a, $b"),
66 [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
64 FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt),
65 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
66 [(op CPU64Regs:$rs, CPU64Regs:$rt)], itin>;
6767 }
6868
6969 // Move from Hi/Lo
7070 let shamt = 0 in {
7171 let rs = 0, rt = 0 in
7272 class MoveFromLOHI64 func, string instr_asm>:
73 FR<0x00, func, (outs CPU64Regs:$dst), (ins),
74 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
73 FR<0x00, func, (outs CPU64Regs:$rd), (ins),
74 !strconcat(instr_asm, "\t$rd"), [], IIHiLo>;
7575
7676 let rt = 0, rd = 0 in
7777 class MoveToLOHI64 func, string instr_asm>:
78 FR<0x00, func, (outs), (ins CPU64Regs:$src),
79 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
78 FR<0x00, func, (outs), (ins CPU64Regs:$rs),
79 !strconcat(instr_asm, "\t$rs"), [], IIHiLo>;
8080 }
8181
8282 // Count Leading Ones/Zeros in Word
8383 class CountLeading64 func, string instr_asm, list pattern>:
84 FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
85 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
84 FR<0x1c, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs),
85 !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
8686 Requires<[HasBitCount]> {
8787 let shamt = 0;
8888 let rt = rd;
179179
180180 /// Count Leading
181181 def DCLZ : CountLeading64<0x24, "dclz",
182 [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
182 [(set CPU64Regs:$rd, (ctlz CPU64Regs:$rs))]>;
183183 def DCLO : CountLeading64<0x25, "dclo",
184 [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
184 [(set CPU64Regs:$rd, (ctlz (not CPU64Regs:$rs)))]>;
185185
186186 //===----------------------------------------------------------------------===//
187187 // Arbitrary patterns that map to one or more instructions
104104 unsigned getRelocation(const MachineInstr &MI,
105105 const MachineOperand &MO) const;
106106
107 unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
108 unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
109 unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
107110 };
108111 }
109112
150153 if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi)
151154 return Mips::reloc_mips_hi;
152155 return Mips::reloc_mips_lo;
156 }
157
158 unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,
159 unsigned OpNo) const {
160 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
161 assert(MI.getOperand(OpNo).isReg());
162 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;
163 return
164 (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;
165 }
166
167 unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI,
168 unsigned OpNo) const {
169 // size is encoded as size-1.
170 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
171 }
172
173 unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI,
174 unsigned OpNo) const {
175 // size is encoded as pos+size-1.
176 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) +
177 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
153178 }
154179
155180 /// getMachineOpValue - Return binary encoding of operand. If the machine
237262 return new MipsCodeEmitter(TM, JCE);
238263 }
239264
240 unsigned MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {
241 // this function will be automatically generated by the CodeEmitterGenerator
242 // using TableGen
243 return 0;
244 }
265 #include "MipsGenCodeEmitter.inc"
7575 // FP load.
7676 class FPLoad op, string opstr, PatFrag FOp, RegisterClass RC,
7777 Operand MemOpnd>:
78 FFI
79 !strconcat(opstr, "\t$ft, $base"), [(set RC:$ft, (FOp addr:$base))]>;
78 FMem
79 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (FOp addr:$addr))],
80 IILoad>;
8081
8182 // FP store.
8283 class FPStore op, string opstr, PatFrag FOp, RegisterClass RC,
8384 Operand MemOpnd>:
84 FFI
85 !strconcat(opstr, "\t$ft, $base"), [(store RC:$ft, addr:$base)]>;
85 FMem
86 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
87 IIStore>;
8688
8789 // Instructions that convert an FP value to 32-bit fixed point.
8890 multiclass FFR1_W_M funct, string opstr> {
157159 // stores, and moves between floating-point and integer registers.
158160 // When defining instructions, we reference all 32-bit registers,
159161 // regardless of register aliasing.
160 let fd = 0 in {
161 /// Move Control Registers From/To CPU Registers
162 def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
162
163 class FFRGPR _fmt, dag outs, dag ins, string asmstr, list pattern>:
164 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
165 bits<5> rt;
166 let ft = rt;
167 let fd = 0;
168 }
169
170 /// Move Control Registers From/To CPU Registers
171 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
163172 "cfc1\t$rt, $fs", []>;
164173
165 def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
166 "ctc1\t$fs, $rt", []>;
167
168 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
174 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
175 "ctc1\t$rt, $fs", []>;
176
177 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
169178 "mfc1\t$rt, $fs",
170179 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
171180
172 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
181 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
173182 "mtc1\t$rt, $fs",
174183 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
175 }
176184
177185 def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
178186 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
202210 }
203211
204212 /// Floating-point Aritmetic
205 defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
213 defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
206214 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
207215 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
208216 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
217225
218226 /// Floating Point Branch of False/True (Likely)
219227 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
220 class FBRANCH : FFI<0x11, (outs),
221 (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
222 [(MipsFPBrcond op, bb:$dst)]>;
223
224 def BC1F : FBRANCH;
225 def BC1T : FBRANCH;
228 class FBRANCH nd, bits<1> tf, PatLeaf op, string asmstr> :
229 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
230 [(MipsFPBrcond op, bb:$dst)]> {
231 let Inst{20-18} = 0;
232 let Inst{17} = nd;
233 let Inst{16} = tf;
234 }
235
236 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
237 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
226238
227239 //===----------------------------------------------------------------------===//
228240 // Floating Point Flag Conditions
248260
249261 /// Floating Point Compare
250262 let Defs=[FCR31] in {
251 def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
263 def FCMP_S32 : FCC<0x10, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
252264 "c.$cc.s\t$fs, $ft",
253265 [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
254266
255 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
267 def FCMP_D32 : FCC<0x11, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
256268 "c.$cc.d\t$fs, $ft",
257269 [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
258270 Requires<[NotFP64bit]>;
286298 defm : MovnPats;
287299 }
288300
289 let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
301 let cc = 0, usesCustomInserter = 1, Uses = [FCR31],
302 Constraints = "$F = $dst" in {
290303 // flag:float, data:int
291304 class CondMovFPInt tf, string instr_asm> :
292305 FCMOV
294307 [(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
295308
296309 // flag:float, data:float
310 let cc = 0 in
297311 class CondMovFPFP fmt, bits<1> tf,
298312 string instr_asm> :
299313 FFCMOV
2020 //
2121 //===----------------------------------------------------------------------===//
2222
23 // Format specifies the encoding used by the instruction. This is part of the
24 // ad-hoc solution used to emit machine instruction encodings by our machine
25 // code emitter.
26 class Format val> {
27 bits<4> Value = val;
28 }
29
30 def Pseudo : Format<0>;
31 def FrmR : Format<1>;
32 def FrmI : Format<2>;
33 def FrmJ : Format<3>;
34 def FrmFR : Format<4>;
35 def FrmFI : Format<5>;
36 def FrmOther : Format<6>; // Instruction w/ a custom format
37
2338 // Generic Mips Format
2439 class MipsInst pattern,
25 InstrItinClass itin>: Instruction
40 InstrItinClass itin, Format f>: Instruction
2641 {
2742 field bits<32> Inst;
43 Format Form = f;
2844
2945 let Namespace = "Mips";
3046
31 bits<6> opcode;
32
33 // Top 5 bits are the 'opcode' field
34 let Inst{31-26} = opcode;
35
36 dag OutOperandList = outs;
37 dag InOperandList = ins;
47 bits<6> Opcode = 0;
48
49 // Top 6 bits are the 'opcode' field
50 let Inst{31-26} = Opcode;
51
52 let OutOperandList = outs;
53 let InOperandList = ins;
3854
3955 let AsmString = asmstr;
4056 let Pattern = pattern;
4157 let Itinerary = itin;
58
59 //
60 // Attributes specific to Mips instructions...
61 //
62 bits<4> FormBits = Form.Value;
63
64 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
65 let TSFlags{3-0} = FormBits;
4266 }
4367
4468 // Mips Pseudo Instructions Format
4569 class MipsPseudo pattern>:
46 MipsInst> {
70 MipsInst, Pseudo> {
71 let isCodeGenOnly = 1;
4772 let isPseudo = 1;
4873 }
4974
5378
5479 class FR op, bits<6> _funct, dag outs, dag ins, string asmstr,
5580 list pattern, InstrItinClass itin>:
56 MipsInst>
81 MipsInst, FrmR>
5782 {
5883 bits<5> rd;
5984 bits<5> rs;
6186 bits<5> shamt;
6287 bits<6> funct;
6388
64 let opcode = op;
89 let Opcode = op;
6590 let funct = _funct;
6691
6792 let Inst{25-21} = rs;
76101 //===----------------------------------------------------------------------===//
77102
78103 class FI op, dag outs, dag ins, string asmstr, list pattern,
79 InstrItinClass itin>: MipsInst>
104 InstrItinClass itin>: MipsInst, FrmI>
80105 {
81106 bits<5> rt;
82107 bits<5> rs;
83108 bits<16> imm16;
84109
85 let opcode = op;
110 let Opcode = op;
86111
87112 let Inst{25-21} = rs;
88113 let Inst{20-16} = rt;
91116
92117 class CBranchBase op, dag outs, dag ins, string asmstr,
93118 list pattern, InstrItinClass itin>:
94 MipsInst>
119 MipsInst, FrmI>
95120 {
96121 bits<5> rs;
97122 bits<5> rt;
98123 bits<16> imm16;
99124
100 let opcode = op;
125 let Opcode = op;
101126
102127 let Inst{25-21} = rs;
103128 let Inst{20-16} = rt;
109134 //===----------------------------------------------------------------------===//
110135
111136 class FJ op, dag outs, dag ins, string asmstr, list pattern,
112 InstrItinClass itin>: MipsInst>
137 InstrItinClass itin>: MipsInst, FrmJ>
113138 {
114139 bits<26> addr;
115140
116 let opcode = op;
141 let Opcode = op;
117142
118143 let Inst{25-0} = addr;
119144 }
137162
138163 class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
139164 string asmstr, list pattern> :
140 MipsInst>
165 MipsInst, FrmFR>
141166 {
142167 bits<5> fd;
143168 bits<5> fs;
145170 bits<5> fmt;
146171 bits<6> funct;
147172
148 let opcode = op;
173 let Opcode = op;
149174 let funct = _funct;
150175 let fmt = _fmt;
151176
161186 //===----------------------------------------------------------------------===//
162187
163188 class FFI op, dag outs, dag ins, string asmstr, list pattern>:
164 MipsInst>
189 MipsInst, FrmFI>
165190 {
166191 bits<5> ft;
167192 bits<5> base;
168193 bits<16> imm16;
169194
170 let opcode = op;
195 let Opcode = op;
171196
172197 let Inst{25-21} = base;
173198 let Inst{20-16} = ft;
179204 //===----------------------------------------------------------------------===//
180205
181206 class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> :
182 MipsInst>
207 MipsInst, FrmOther>
183208 {
184209 bits<5> fs;
185210 bits<5> ft;
186211 bits<4> cc;
187212 bits<5> fmt;
188213
189 let opcode = 0x11;
214 let Opcode = 0x11;
190215 let fmt = _fmt;
191216
192217 let Inst{25-21} = fmt;
200225
201226 class FCMOV _tf, dag outs, dag ins, string asmstr,
202227 list pattern> :
203 MipsInst>
228 MipsInst, FrmOther>
204229 {
205230 bits<5> rd;
206231 bits<5> rs;
207 bits<3> N;
232 bits<3> cc;
208233 bits<1> tf;
209234
210 let opcode = 0;
235 let Opcode = 0;
211236 let tf = _tf;
212237
213238 let Inst{25-21} = rs;
214 let Inst{20-18} = N;
239 let Inst{20-18} = cc;
215240 let Inst{17} = 0;
216241 let Inst{16} = tf;
217242 let Inst{15-11} = rd;
221246
222247 class FFCMOV _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
223248 list pattern> :
224 MipsInst>
249 MipsInst, FrmOther>
225250 {
226251 bits<5> fd;
227252 bits<5> fs;
228 bits<3> N;
253 bits<3> cc;
229254 bits<5> fmt;
230255 bits<1> tf;
231256
232 let opcode = 17;
257 let Opcode = 17;
233258 let fmt = _fmt;
234259 let tf = _tf;
235260
236261 let Inst{25-21} = fmt;
237 let Inst{20-18} = N;
262 let Inst{20-18} = cc;
238263 let Inst{17} = 0;
239264 let Inst{16} = tf;
240265 let Inst{15-11} = fs;
152152 def mem : Operand {
153153 let PrintMethod = "printMemOperand";
154154 let MIOperandInfo = (ops CPURegs, simm16);
155 let EncoderMethod = "getMemEncoding";
155156 }
156157
157158 def mem64 : Operand {
162163 def mem_ea : Operand {
163164 let PrintMethod = "printMemOperandEA";
164165 let MIOperandInfo = (ops CPURegs, simm16);
166 let EncoderMethod = "getMemEncoding";
167 }
168
169 // size operand of ext instruction
170 def size_ext : Operand {
171 let EncoderMethod = "getSizeExtEncoding";
172 }
173
174 // size operand of ins instruction
175 def size_ins : Operand {
176 let EncoderMethod = "getSizeInsEncoding";
165177 }
166178
167179 // Transformation Function - get the lower 16 bits.
270282 // Arithmetic and logical instructions with 2 register operands.
271283 class ArithLogicI op, string instr_asm, SDNode OpNode,
272284 Operand Od, PatLeaf imm_type, RegisterClass RC> :
273 FI
274 !strconcat(instr_asm, "\t$rt, $rs, $i"),
275 [(set RC:$rt, (OpNode RC:$rs, imm_type:$i))], IIAlu>;
285 FI
286 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
287 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
276288
277289 class ArithOverflowI op, string instr_asm, SDNode OpNode,
278290 Operand Od, PatLeaf imm_type, RegisterClass RC> :
279 FI
280 !strconcat(instr_asm, "\t$rt, $rs, $i"), [], IIAlu>;
291 FI
292 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
281293
282294 // Arithmetic Multiply ADD/SUB
283295 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
318330
319331 // Load Upper Imediate
320332 class LoadUpper op, string instr_asm>:
321 FI
322 !strconcat(instr_asm, "\t$rt, $imm"), [], IIAlu> {
333 FI
334 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
323335 let rs = 0;
336 }
337
338 class FMem op, dag outs, dag ins, string asmstr, list pattern,
339 InstrItinClass itin>: FFI {
340 bits<21> addr;
341 let Inst{25-21} = addr{20-16};
342 let Inst{15-0} = addr{15-0};
324343 }
325344
326345 // Memory Load/Store
327346 let canFoldAsLoad = 1 in
328347 class LoadM op, string instr_asm, PatFrag OpNode, RegisterClass RC,
329348 Operand MemOpnd, bit Pseudo>:
330 FI
349 FMem
331350 !strconcat(instr_asm, "\t$rt, $addr"),
332351 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
333352 let isPseudo = Pseudo;
335354
336355 class StoreM op, string instr_asm, PatFrag OpNode, RegisterClass RC,
337356 Operand MemOpnd, bit Pseudo>:
338 FI
357 FMem
339358 !strconcat(instr_asm, "\t$rt, $addr"),
340359 [(OpNode RC:$rt, addr:$addr)], IIStore> {
341360 let isPseudo = Pseudo;
379398
380399 // Conditional Branch
381400 class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
382 CBranchBase
383 !strconcat(instr_asm, "\t$rs, $rt, $offset"),
384 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch> {
401 CBranchBase
402 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
403 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
385404 let isBranch = 1;
386405 let isTerminator = 1;
387406 let hasDelaySlot = 1;
389408
390409 class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op,
391410 RegisterClass RC>:
392 CBranchBase
393 !strconcat(instr_asm, "\t$rs, $offset"),
394 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch> {
411 CBranchBase
412 !strconcat(instr_asm, "\t$rs, $imm16"),
413 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
395414 let rt = _rt;
396415 let isBranch = 1;
397416 let isTerminator = 1;
410429
411430 class SetCC_I op, string instr_asm, PatFrag cond_op, Operand Od,
412431 PatLeaf imm_type, RegisterClass RC>:
413 FI
414 !strconcat(instr_asm, "\t$rd, $rs, $i"),
415 [(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
432 FI,
433 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
434 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
416435 IIAlu>;
417436
418437 // Unconditional branch
449468 }
450469
451470 class BranchLink:
452 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
453 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> {
454 let rt = 0;
455 }
471 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops),
472 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
456473 }
457474
458475 // Mul, Div
492509 }
493510
494511 class EffectiveAddress :
495 FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
512 FMem<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
496513 instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
497514
498515 // Count Leading Ones/Zeros in Word
506523
507524 // Sign Extend in Register.
508525 class SignExtInReg sa, string instr_asm, ValueType vt>:
509 FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
526 FR<0x1f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
510527 !strconcat(instr_asm, "\t$rd, $rt"),
511528 [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
512529 let rs = 0;
684701
685702 let hasSideEffects = 1 in
686703 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
687 [(MipsSync imm:$stype)], NoItinerary>
704 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
688705 {
689 let opcode = 0;
706 bits<5> stype;
707 let Opcode = 0;
690708 let Inst{25-11} = 0;
709 let Inst{10-6} = stype;
691710 let Inst{5-0} = 15;
692711 }
693712
694713 /// Load-linked, Store-conditional
695714 let mayLoad = 1 in
696 def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
697 "ll\t$dst, $addr", [], IILoad>;
698 let mayStore = 1, Constraints = "$src = $dst" in
699 def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
700 "sc\t$src, $addr", [], IIStore>;
715 def LL : FMem<0x30, (outs CPURegs:$rt), (ins mem:$addr),
716 "ll\t$rt, $addr", [], IILoad>;
717 let mayStore = 1, Constraints = "$rt = $dst" in
718 def SC : FMem<0x38, (outs CPURegs:$dst), (ins CPURegs:$rt, mem:$addr),
719 "sc\t$rt, $addr", [], IIStore>;
701720
702721 /// Jump and Branch Instructions
703722 def J : JumpFJ<0x02, "j">;
709728 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
710729 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
711730 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
712 def BLEZ : CBranchZero<0x07, 0, "blez", setle, CPURegs>;
731 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
713732 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
714733
715 def BGEZAL : BranchLink<"bgezal">;
716 def BLTZAL : BranchLink<"bltzal">;
734 let rt=0x11 in
735 def BGEZAL : BranchLink<"bgezal">;
736 let rt=0x10 in
737 def BLTZAL : BranchLink<"bltzal">;
717738
718739 let isReturn=1, isTerminator=1, hasDelaySlot=1,
719 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
720 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
740 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
741 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
721742 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
722743
723744 /// Multiply and Divide Instructions.
796817 def RDHWR : ReadHardware;
797818
798819 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
799 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
820 (ins CPURegs:$rs, uimm16:$pos, size_ext:$sz),
800821 [(set CPURegs:$rt,
801822 (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
802823 NoItinerary>;
803824
804825 let Constraints = "$src = $rt" in
805826 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
806 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
827 (ins CPURegs:$rs, uimm16:$pos, size_ins:$sz, CPURegs:$src),
807828 [(set CPURegs:$rt,
808829 (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
809830 CPURegs:$src))],
5656 ".globl " ASMPREFIX "MipsCompilationCallback\n"
5757 ASMPREFIX "MipsCompilationCallback:\n"
5858 ".ent " ASMPREFIX "MipsCompilationCallback\n"
59 ".frame $29, 32, $31\n"
59 ".frame $sp, 32, $ra\n"
6060 ".set noreorder\n"
6161 ".cpload $t9\n"
6262
63 "addiu $sp, $sp, -60\n"
63 "addiu $sp, $sp, -64\n"
6464 ".cprestore 16\n"
6565
6666 // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain
7575 "sw $a3, 32($sp)\n"
7676 "sw $ra, 36($sp)\n"
7777 "sw $t8, 40($sp)\n"
78 "sdc1 $f12, 44($sp)\n"
79 "sdc1 $f14, 52($sp)\n"
78 "sdc1 $f12, 48($sp)\n"
79 "sdc1 $f14, 56($sp)\n"
8080
8181 // t8 points at the end of function stub. Pass the beginning of the stub
8282 // to the MipsCompilationCallbackC.
9191 "lw $a3, 32($sp)\n"
9292 "lw $ra, 36($sp)\n"
9393 "lw $t8, 40($sp)\n"
94 "ldc1 $f12, 44($sp)\n"
95 "ldc1 $f14, 52($sp)\n"
96 "addiu $sp, $sp, 60\n"
94 "ldc1 $f12, 48($sp)\n"
95 "ldc1 $f14, 56($sp)\n"
96 "addiu $sp, $sp, 64\n"
9797
9898 // Jump to the (newly modified) stub to invoke the real function.
9999 "addiu $t8, $t8, -16\n"