llvm.org GIT mirror llvm / 026a108
Merging r356039: ------------------------------------------------------------------------ r356039 | atanasyan | 2019-03-13 04:04:38 -0700 (Wed, 13 Mar 2019) | 11 lines [MIPS][microMIPS] Fix PseudoMTLOHI_MM matching and expansion On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless of +dsp argument. This patch checks is HasDSP predicate is present for PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate. Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair. Patch by Mirko Brkusanin. Differential Revision: http://reviews.llvm.org/D59203 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@358941 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 months ago
3 changed file(s) with 69 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
13131313 def PseudoPICK_PH : PseudoPICK;
13141314 def PseudoPICK_QB : PseudoPICK;
13151315
1316 def PseudoMTLOHI_DSP : PseudoMTLOHI;
1316 let AdditionalPredicates = [HasDSP] in {
1317 def PseudoMTLOHI_DSP : PseudoMTLOHI;
1318 }
13171319
13181320 // Patterns.
13191321 class DSPPat :
445445 break;
446446 case Mips::PseudoMTLOHI_DSP:
447447 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
448 break;
449 case Mips::PseudoMTLOHI_MM:
450 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
448451 break;
449452 case Mips::PseudoCVT_S_W:
450453 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\
2 ; RUN: FileCheck %s -check-prefixes=MMR2
3 ; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\
4 ; RUN: FileCheck %s -check-prefixes=MMR2-DSP
5
6 define i64 @test(i32 signext %a, i32 signext %b) {
7 ; MMR2-LABEL: test:
8 ; MMR2: # %bb.0: # %entry
9 ; MMR2-NEXT: li16 $2, 0 #
10 ; MMR2-NEXT: #
11 ; MMR2-NEXT: # >
12 ; MMR2-NEXT: li16 $3, 1 #
13 ; MMR2-NEXT: #
14 ; MMR2-NEXT: # >
15 ; MMR2-NEXT: mtlo $3 #
16 ; MMR2-NEXT: # >
17 ; MMR2-NEXT: mthi $2 #
18 ; MMR2-NEXT: # >
19 ; MMR2-NEXT: madd $4, $5 #
20 ; MMR2-NEXT: #
21 ; MMR2-NEXT: # >
22 ; MMR2-NEXT: mflo16 $2 #
23 ; MMR2-NEXT: # >
24 ; MMR2-NEXT: mfhi16 $3 #
25 ; MMR2-NEXT: # >
26 ; MMR2-NEXT: jrc $ra #
27 ; MMR2-NEXT: # >
28 ;
29 ; MMR2-DSP-LABEL: test:
30 ; MMR2-DSP: # %bb.0: # %entry
31 ; MMR2-DSP-NEXT: li16 $2, 0 #
32 ; MMR2-DSP-NEXT: #
33 ; MMR2-DSP-NEXT: # >
34 ; MMR2-DSP-NEXT: li16 $3, 1 #
35 ; MMR2-DSP-NEXT: #
36 ; MMR2-DSP-NEXT: # >
37 ; MMR2-DSP-NEXT: mtlo $3, $ac0 #
38 ; MMR2-DSP-NEXT: #
39 ; MMR2-DSP-NEXT: # >
40 ; MMR2-DSP-NEXT: mthi $2, $ac0 #
41 ; MMR2-DSP-NEXT: #
42 ; MMR2-DSP-NEXT: # >
43 ; MMR2-DSP-NEXT: madd $ac0, $4, $5 #
44 ; MMR2-DSP-NEXT: #
45 ; MMR2-DSP-NEXT: #
46 ; MMR2-DSP-NEXT: #
47 ; MMR2-DSP-NEXT: # >
48 ; MMR2-DSP-NEXT: mflo $2, $ac0 #
49 ; MMR2-DSP-NEXT: #
50 ; MMR2-DSP-NEXT: # >
51 ; MMR2-DSP-NEXT: jr $ra #
52 ; MMR2-DSP-NEXT: # >
53 ; MMR2-DSP-NEXT: mfhi $3, $ac0 #
54 ; MMR2-DSP-NEXT: #
55 ; MMR2-DSP-NEXT: # >
56 entry:
57 %conv = sext i32 %a to i64
58 %conv1 = sext i32 %b to i64
59 %mul = mul nsw i64 %conv, %conv1
60 %add = add nsw i64 %mul, 1
61 ret i64 %add
62 }