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add CHECK-LABELs for better reliability git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231962 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 5 years ago
1 changed file(s) with 24 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
22 ; We don't check any vinsertf128 variant with immediate 0 because that's just a blend.
33
44 define <4 x double> @test_x86_avx_vinsertf128_pd_256_1(<4 x double> %a0, <2 x double> %a1) {
5 ; CHECK-LABEL: test_x86_avx_vinsertf128_pd_256_1:
6 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
5 ; CHECK-LABEL: test_x86_avx_vinsertf128_pd_256_1:
6 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
77 %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 1)
88 ret <4 x double> %res
99 }
1010 declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
1111
1212 define <8 x float> @test_x86_avx_vinsertf128_ps_256_1(<8 x float> %a0, <4 x float> %a1) {
13 ; CHECK-LABEL: test_x86_avx_vinsertf128_ps_256_1:
14 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
13 ; CHECK-LABEL: test_x86_avx_vinsertf128_ps_256_1:
14 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
1515 %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 1)
1616 ret <8 x float> %res
1717 }
1818 declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
1919
2020 define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1) {
21 ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_1:
22 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
21 ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_1:
22 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2323 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 1)
2424 ret <8 x i32> %res
2525 }
2828 ; of a vinsertf128 $0 which should be optimized into a blend, so just check that it's
2929 ; not a vinsertf128 $1.
3030 define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) {
31 ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2:
32 ; CHECK-NOT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
31 ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2:
32 ; CHECK-NOT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
3333 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 2)
3434 ret <8 x i32> %res
3535 }
3636 declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
3737
3838 define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
39 ; CHECK: vblendpd
39 ; CHECK-LABEL: test_x86_avx_blend_pd_256:
40 ; CHECK: vblendpd
4041 %res = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 7) ; <<4 x double>> [#uses=1]
4142 ret <4 x double> %res
4243 }
4445
4546
4647 define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
47 ; CHECK: vblendps
48 ; CHECK-LABEL: test_x86_avx_blend_ps_256:
49 ; CHECK: vblendps
4850 %res = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
4951 ret <8 x float> %res
5052 }
5254
5355
5456 define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
55 ; CHECK: vdpps
57 ; CHECK-LABEL: test_x86_avx_dp_ps_256:
58 ; CHECK: vdpps
5659 %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
5760 ret <8 x float> %res
5861 }
6063
6164
6265 define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) {
63 ; CHECK: vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
66 ; CHECK-LABEL: test_x86_sse2_psll_dq:
67 ; CHECK: vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
6468 %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
6569 ret <2 x i64> %res
6670 }
6872
6973
7074 define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) {
71 ; CHECK: vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
75 ; CHECK-LABEL: test_x86_sse2_psrl_dq:
76 ; CHECK: vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
7277 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
7378 ret <2 x i64> %res
7479 }
7681
7782
7883 define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
79 ; CHECK: vblendpd
84 ; CHECK-LABEL: test_x86_sse41_blendpd:
85 ; CHECK: vblendpd
8086 %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i8 2) ; <<2 x double>> [#uses=1]
8187 ret <2 x double> %res
8288 }
8490
8591
8692 define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) {
87 ; CHECK: vblendps
93 ; CHECK-LABEL: test_x86_sse41_blendps:
94 ; CHECK: vblendps
8895 %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
8996 ret <4 x float> %res
9097 }
9299
93100
94101 define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
95 ; CHECK: vpblendw
102 ; CHECK-LABEL: test_x86_sse41_pblendw:
103 ; CHECK: vpblendw
96104 %res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7) ; <<8 x i16>> [#uses=1]
97105 ret <8 x i16> %res
98106 }