llvm.org GIT mirror llvm / 01d98c6
AMDGPU: Don't re-get the subtarget It's already available in the class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375363 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 1 year, 1 month ago
1 changed file(s) with 9 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
107107
108108 unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
109109 const MachineFunction &MF) const {
110
111 const GCNSubtarget &ST = MF.getSubtarget();
112110 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
113111 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
114112 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
133131
134132 unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg(
135133 const MachineFunction &MF) const {
136 const GCNSubtarget &ST = MF.getSubtarget();
137134 unsigned Reg = findPrivateSegmentWaveByteOffsetRegIndex(ST.getMaxNumSGPRs(MF));
138135 return AMDGPU::SGPR_32RegClass.getRegister(Reg);
139136 }
191188 Reserved.set(AMDGPU::VCC_HI);
192189 }
193190
194 const GCNSubtarget &ST = MF.getSubtarget();
195
196191 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
197192 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
198193 for (unsigned i = MaxNumSGPRs; i < TotalNumSGPRs; ++i) {
354349 DL = Ins->getDebugLoc();
355350
356351 MachineFunction *MF = MBB->getParent();
357 const GCNSubtarget &Subtarget = MF->getSubtarget();
358 const SIInstrInfo *TII = Subtarget.getInstrInfo();
352 const SIInstrInfo *TII = ST.getInstrInfo();
359353
360354 if (Offset == 0) {
361355 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
384378
385379 MachineBasicBlock *MBB = MI.getParent();
386380 MachineFunction *MF = MBB->getParent();
387 const GCNSubtarget &Subtarget = MF->getSubtarget();
388 const SIInstrInfo *TII = Subtarget.getInstrInfo();
381 const SIInstrInfo *TII = ST.getInstrInfo();
389382
390383 #ifndef NDEBUG
391384 // FIXME: Is it possible to be storing a frame index to itself?
545538 }
546539 }
547540
548 static MachineInstrBuilder spillVGPRtoAGPR(MachineBasicBlock::iterator MI,
541 static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST,
542 MachineBasicBlock::iterator MI,
549543 int Index,
550544 unsigned Lane,
551545 unsigned ValueReg,
553547 MachineBasicBlock *MBB = MI->getParent();
554548 MachineFunction *MF = MI->getParent()->getParent();
555549 SIMachineFunctionInfo *MFI = MF->getInfo();
556 const GCNSubtarget &ST = MF->getSubtarget();
557550 const SIInstrInfo *TII = ST.getInstrInfo();
558551
559552 MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
576569
577570 // This differs from buildSpillLoadStore by only scavenging a VGPR. It does not
578571 // need to handle the case where an SGPR may need to be spilled while spilling.
579 static bool buildMUBUFOffsetLoadStore(const SIInstrInfo *TII,
572 static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST,
580573 MachineFrameInfo &MFI,
581574 MachineBasicBlock::iterator MI,
582575 int Index,
583576 int64_t Offset) {
577 const SIInstrInfo *TII = ST.getInstrInfo();
584578 MachineBasicBlock *MBB = MI->getParent();
585579 const DebugLoc &DL = MI->getDebugLoc();
586580 bool IsStore = MI->mayStore();
592586 return false;
593587
594588 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata);
595 if (spillVGPRtoAGPR(MI, Index, 0, Reg->getReg(), false).getInstr())
589 if (spillVGPRtoAGPR(ST, MI, Index, 0, Reg->getReg(), false).getInstr())
596590 return true;
597591
598592 MachineInstrBuilder NewMI =
627621 RegScavenger *RS) const {
628622 MachineBasicBlock *MBB = MI->getParent();
629623 MachineFunction *MF = MI->getParent()->getParent();
630 const GCNSubtarget &ST = MF->getSubtarget();
631624 const SIInstrInfo *TII = ST.getInstrInfo();
632625 const MachineFrameInfo &MFI = MF->getFrameInfo();
633626
701694 SrcDstRegState |= getKillRegState(IsKill);
702695 }
703696
704 auto MIB = spillVGPRtoAGPR(MI, Index, i, SubReg, IsKill);
697 auto MIB = spillVGPRtoAGPR(ST, MI, Index, i, SubReg, IsKill);
705698
706699 if (!MIB.getInstr()) {
707700 unsigned FinalReg = SubReg;
762755 if (OnlyToVGPR && !SpillToVGPR)
763756 return false;
764757
765 const GCNSubtarget &ST = MF->getSubtarget();
766758 const SIInstrInfo *TII = ST.getInstrInfo();
767759
768760 Register SuperReg = MI->getOperand(0).getReg();
881873 return false;
882874
883875 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
884 const GCNSubtarget &ST = MF->getSubtarget();
885876 const SIInstrInfo *TII = ST.getInstrInfo();
886877 const DebugLoc &DL = MI->getDebugLoc();
887878
994985 MachineBasicBlock *MBB = MI->getParent();
995986 SIMachineFunctionInfo *MFI = MF->getInfo();
996987 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
997 const GCNSubtarget &ST = MF->getSubtarget();
998988 const SIInstrInfo *TII = ST.getInstrInfo();
999989 DebugLoc DL = MI->getDebugLoc();
1000990
12221212 int64_t NewOffset = OldImm + Offset;
12231213
12241214 if (isUInt<12>(NewOffset) &&
1225 buildMUBUFOffsetLoadStore(TII, FrameInfo, MI, Index, NewOffset)) {
1215 buildMUBUFOffsetLoadStore(ST, FrameInfo, MI, Index, NewOffset)) {
12261216 MI->eraseFromParent();
12271217 return;
12281218 }
17401730
17411731 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
17421732 MachineFunction &MF) const {
1743
1744 const GCNSubtarget &ST = MF.getSubtarget();
17451733 const SIMachineFunctionInfo *MFI = MF.getInfo();
17461734
17471735 unsigned Occupancy = ST.getOccupancyWithLocalMemSize(MFI->getLDSSize(),