llvm.org GIT mirror llvm / 01c06d7
AArch64: add support for llvm.aarch64.hint intrinsic This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to support the various hint intrinsic functions in the ACLE. Add an optional pattern field that permits the subclass to specify the pattern that matches the selection. The intrinsic pattern is set as mayLoad, mayStore, so overload the value for the definition of the hint instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212883 91177308-0d34-0410-b5e6-96231b3b80d8 Saleem Abdulrasool 6 years ago
3 changed file(s) with 89 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
3030 LLVMMatchType<0>], [IntrNoMem]>;
3131 def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
3232 LLVMMatchType<0>], [IntrNoMem]>;
33
34 //===----------------------------------------------------------------------===//
35 // HINT
36
37 def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>;
3338
3439 //===----------------------------------------------------------------------===//
3540 // RBIT
775775
776776 // Base encoding for system instruction operands.
777777 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
778 class BaseSystemI
779 : I {
778 class BaseSystemI
779 list pattern = []>
780 : I {
780781 let Inst{31-22} = 0b1101010100;
781782 let Inst{21} = L;
782783 }
783784
784785 // System instructions which do not have an Rt register.
785 class SimpleSystemI
786 : BaseSystemI {
786 class SimpleSystemI
787 list pattern = []>
788 : BaseSystemI {
787789 let Inst{4-0} = 0b11111;
788790 }
789791
796798 }
797799
798800 // Hint instructions that take both a CRm and a 3-bit immediate.
799 class HintI
800 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
801 Sched<[WriteHint]> {
802 bits <7> imm;
803 let Inst{20-12} = 0b000110010;
804 let Inst{11-5} = imm;
805 }
801 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
802 // model patterns with sufficiently fine granularity
803 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
804 class HintI
805 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "",
806 [(int_aarch64_hint imm0_127:$imm)]>,
807 Sched<[WriteHint]> {
808 bits <7> imm;
809 let Inst{20-12} = 0b000110010;
810 let Inst{11-5} = imm;
811 }
806812
807813 // System instructions taking a single literal operand which encodes into
808814 // CRm. op2 differentiates the opcodes.
0 ; RUN: llc -mtriple aarch64-eabi -o - %s | FileCheck %s
1
2 declare void @llvm.aarch64.hint(i32) nounwind
3
4 define void @hint_nop() {
5 entry:
6 tail call void @llvm.aarch64.hint(i32 0) nounwind
7 ret void
8 }
9
10 ; CHECK-LABEL: hint_nop
11 ; CHECK: nop
12
13 define void @hint_yield() {
14 entry:
15 tail call void @llvm.aarch64.hint(i32 1) nounwind
16 ret void
17 }
18
19 ; CHECK-LABEL: hint_yield
20 ; CHECK: yield
21
22 define void @hint_wfe() {
23 entry:
24 tail call void @llvm.aarch64.hint(i32 2) nounwind
25 ret void
26 }
27
28 ; CHECK-LABEL: hint_wfe
29 ; CHECK: wfe
30
31 define void @hint_wfi() {
32 entry:
33 tail call void @llvm.aarch64.hint(i32 3) nounwind
34 ret void
35 }
36
37 ; CHECK-LABEL: hint_wfi
38 ; CHECK: wfi
39
40 define void @hint_sev() {
41 entry:
42 tail call void @llvm.aarch64.hint(i32 4) nounwind
43 ret void
44 }
45
46 ; CHECK-LABEL: hint_sev
47 ; CHECK: sev
48
49 define void @hint_sevl() {
50 entry:
51 tail call void @llvm.aarch64.hint(i32 5) nounwind
52 ret void
53 }
54
55 ; CHECK-LABEL: hint_sevl
56 ; CHECK: sevl
57
58 define void @hint_undefined() {
59 entry:
60 tail call void @llvm.aarch64.hint(i32 8) nounwind
61 ret void
62 }
63
64 ; CHECK-LABEL: hint_undefined
65 ; CHECK: hint #0x8
66