llvm.org GIT mirror llvm / 01a2efa
Merging r168837: into the 3.2 release branch. Avoid rewriting instructions twice. This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). <rdar://problem/12758887> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168849 91177308-0d34-0410-b5e6-96231b3b80d8 Pawel Wodnicki 6 years ago
2 changed file(s) with 50 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
849849 // Update LiveDebugVariables.
850850 LDV->renameRegister(SrcReg, DstReg, SubIdx);
851851
852 SmallPtrSet Visited;
852853 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
853854 MachineInstr *UseMI = I.skipInstruction();) {
855 // Each instruction can only be rewritten once because sub-register
856 // composition is not always idempotent. When SrcReg != DstReg, rewriting
857 // the UseMI operands removes them from the SrcReg use-def chain, but when
858 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
859 // operands mentioning the virtual register.
860 if (SrcReg == DstReg && !Visited.insert(UseMI))
861 continue;
862
854863 SmallVector Ops;
855864 bool Reads, Writes;
856865 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
316316 store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128
317317 ret void
318318 }
319
320 ;
321 ; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than
322 ; once under rare circumstances. When widening a register from QPR to DTriple
323 ; with the original virtual register in dsub_1_dsub_2, the double rewrite would
324 ; produce an invalid sub-register.
325 ;
326 ; This is because dsub_1_dsub_2 is not an idempotent sub-register index.
327 ; It will translate %vr:dsub_0 -> %vr:dsub_1.
328 define hidden fastcc void @radar12758887() nounwind optsize ssp {
329 entry:
330 br i1 undef, label %for.body, label %for.end70
331
332 for.body: ; preds = %for.end, %entry
333 br i1 undef, label %for.body29, label %for.end
334
335 for.body29: ; preds = %for.body29, %for.body
336 %0 = load <2 x double>* null, align 1
337 %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
338 %mul41 = fmul <2 x double> undef, %splat40
339 %add42 = fadd <2 x double> undef, %mul41
340 %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32>
341 %mul45 = fmul <2 x double> undef, %splat44
342 %add46 = fadd <2 x double> undef, %mul45
343 br i1 undef, label %for.end, label %for.body29
344
345 for.end: ; preds = %for.body29, %for.body
346 %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]
347 %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]
348 %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32>
349 %add58 = fadd <2 x double> undef, %1
350 %mul61 = fmul <2 x double> %add58, undef
351 %add63 = fadd <2 x double> undef, %mul61
352 %add64 = fadd <2 x double> undef, %add63
353 %add67 = fadd <2 x double> undef, %add64
354 store <2 x double> %add67, <2 x double>* undef, align 1
355 br i1 undef, label %for.end70, label %for.body
356
357 for.end70: ; preds = %for.end, %entry
358 ret void
359 }