llvm.org GIT mirror llvm / 013ed4a
Remove the need to cache the subtarget in the Sparc TargetRegisterInfo classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232013 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 4 years ago
4 changed file(s) with 11 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
3232 void SparcInstrInfo::anchor() {}
3333
3434 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
35 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
36 RI(ST), Subtarget(ST) {
37 }
35 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
36 Subtarget(ST) {}
3837
3938 /// isLoadFromStackSlot - If the specified machine instruction is a direct
4039 /// load from a stack slot, return the virtual or physical register number of
2020 #include "SparcGenInstrInfo.inc"
2121
2222 namespace llvm {
23
24 class SparcSubtarget;
2325
2426 /// SPII - This namespace holds all of the target specific flags that
2527 /// instruction info tracks.
3333 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
3434 cl::desc("Reserve application registers (%g2-%g4)"));
3535
36 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
37 : SparcGenRegisterInfo(SP::O7), Subtarget(st) {
38 }
36 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
3937
4038 const MCPhysReg*
4139 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
5553
5654 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
5755 BitVector Reserved(getNumRegs());
56 const SparcSubtarget &Subtarget = MF.getSubtarget();
5857 // FIXME: G1 reserved for now for large imm generation by frame code.
5958 Reserved.set(SP::G1);
6059
8988 const TargetRegisterClass*
9089 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
9190 unsigned Kind) const {
91 const SparcSubtarget &Subtarget = MF.getSubtarget();
9292 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
9393 }
9494
160160
161161 // Addressable stack objects are accessed using neg. offsets from %fp
162162 MachineFunction &MF = *MI.getParent()->getParent();
163 const SparcSubtarget &Subtarget = MF.getSubtarget();
163164 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
164165 MI.getOperand(FIOperandNum + 1).getImm() +
165166 Subtarget.getStackPointerBias();
174175
175176 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
176177 if (MI.getOpcode() == SP::STQFri) {
177 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
178 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
178179 unsigned SrcReg = MI.getOperand(2).getReg();
179180 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
180181 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
186187 MI.getOperand(2).setReg(SrcOddReg);
187188 Offset += 8;
188189 } else if (MI.getOpcode() == SP::LDQFri) {
189 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
190 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
190191 unsigned DestReg = MI.getOperand(0).getReg();
191192 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
192193 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
2020
2121 namespace llvm {
2222
23 class SparcSubtarget;
2423 class TargetInstrInfo;
2524 class Type;
2625
2726 struct SparcRegisterInfo : public SparcGenRegisterInfo {
28 SparcSubtarget &Subtarget;
29
30 SparcRegisterInfo(SparcSubtarget &st);
27 SparcRegisterInfo();
3128
3229 /// Code Generation virtual methods...
3330 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;