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[Hexagon] Add trap1 instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326492 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 2 years ago
6 changed file(s) with 73 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
13321332 }
13331333 break;
13341334
1335 case Hexagon::J2_trap1:
1336 if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
1337 MCOperand &Rx = Inst.getOperand(0);
1338 MCOperand &Ry = Inst.getOperand(1);
1339 if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) {
1340 Error(IDLoc, "trap1 can only have register r0 as operand");
1341 return Match_InvalidOperand;
1342 }
1343 }
1344 break;
1345
13351346 case Hexagon::A2_iconst: {
13361347 Inst.setOpcode(Hexagon::A2_addi);
13371348 MCOperand Reg = Inst.getOperand(0);
7878 def tc_56d25411 : InstrItinClass;
7979 def tc_57288781 : InstrItinClass;
8080 def tc_594ab548 : InstrItinClass;
81 def tc_59a01ead : InstrItinClass;
8182 def tc_5acef64a : InstrItinClass;
8283 def tc_5ba5997d : InstrItinClass;
8384 def tc_5eb851fc : InstrItinClass;
262263 InstrItinData ]>,
263264 InstrItinData ]>,
264265 InstrItinData ]>,
266 InstrItinData ]>,
265267 InstrItinData ]>,
266268 InstrItinData ]>,
267269 InstrItinData ]>,
447449 InstrItinData ]>,
448450 InstrItinData ]>,
449451 InstrItinData ]>,
452 InstrItinData ]>,
450453 InstrItinData ]>,
451454 InstrItinData ]>,
452455 InstrItinData ]>,
839842 [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
840843 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
841844
845 InstrItinData
846 [InstrStage<1, [SLOT2]>], [3, 2, 2],
847 [Hex_FWD, Hex_FWD, Hex_FWD]>,
848
842849 InstrItinData
843850 [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
844851 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
15671574 [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
15681575 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
15691576
1577 InstrItinData
1578 [InstrStage<1, [SLOT2]>], [3, 2, 2],
1579 [Hex_FWD, Hex_FWD, Hex_FWD]>,
1580
15701581 InstrItinData
15711582 [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
15721583 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
23102321 [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
23112322 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
23122323
2324 InstrItinData
2325 [InstrStage<1, [SLOT2], 0>,
2326 InstrStage<1, [CVI_ST]>], [3, 2, 2],
2327 [Hex_FWD, Hex_FWD, Hex_FWD]>,
2328
23132329 InstrItinData
23142330 [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
23152331 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
30563072 [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
30573073 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
30583074
3075 InstrItinData
3076 [InstrStage<1, [SLOT2]>], [3, 2, 2],
3077 [Hex_FWD, Hex_FWD, Hex_FWD]>,
3078
30593079 InstrItinData
30603080 [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
30613081 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
37843804 [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
37853805 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
37863806
3807 InstrItinData
3808 [InstrStage<1, [SLOT2]>], [4, 1, 2],
3809 [Hex_FWD, Hex_FWD, Hex_FWD]>,
3810
37873811 InstrItinData
37883812 [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
37893813 [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
56675667 let Inst{13-13} = 0b0;
56685668 let Inst{31-16} = 0b0101010000000000;
56695669 let isSolo = 1;
5670 }
5671 def J2_trap1 : HInst<
5672 (outs IntRegs:$Rx32),
5673 (ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5674 "trap1($Rx32,#$Ii)",
5675 tc_59a01ead, TypeJ>, Enc_33f8ba {
5676 let Inst{1-0} = 0b00;
5677 let Inst{7-5} = 0b000;
5678 let Inst{13-13} = 0b0;
5679 let Inst{31-21} = 0b01010100100;
5680 let hasNewValue = 1;
5681 let opNewValue = 0;
5682 let isSolo = 1;
5683 let Uses = [GOSP];
5684 let Defs = [GOSP, PC];
5685 let Constraints = "$Rx32 = $Rx32in";
5686 }
5687 def J2_trap1_noregmap : HInst<
5688 (outs),
5689 (ins u8_0Imm:$Ii),
5690 "trap1(#$Ii)",
5691 tc_59a01ead, TypeMAPPING> {
5692 let isPseudo = 1;
5693 let isCodeGenOnly = 1;
56705694 }
56715695 def J4_cmpeq_f_jumpnv_nt : HInst<
56725696 (outs),
2525 def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>;
2626 def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>;
2727 def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>;
28 def J2_trap1_noregmapAlias : InstAlias<"trap1(#$Ii)", (J2_trap1 R0, u8_0Imm:$Ii)>;
2829 def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32 = memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
2930 def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32 = memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
3031 def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32 = membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
0 # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
1 # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V65
2
3 # CHECK-V62: trap1(r0,#0)
4 # CHECK-V65: trap1(r0,#0)
5 trap1(#0)
None # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
0 # RUN: llvm-mc -triple=hexagon -mv65 -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
11 # Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER
22
33 # Load locked
5656
5757 # CHECK: 18 df 00 54
5858 trap0(#254)
59
60 # CHECK: 14 df 80 54
61 trap1(r0, #253)
62
63 # CHECK: 14 df 80 54
64 trap1(#253)