llvm.org GIT mirror llvm / 00d3dda
Don't call tablegen'ed Predicate_* functions in the ARM target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
3 changed file(s) with 15 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
116116 SDValue &OffImm);
117117 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
118118 SDValue &OffReg, SDValue &ShImm);
119
120 inline bool Pred_so_imm(SDNode *inN) const {
121 ConstantSDNode *N = cast(inN);
122 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
123 }
124
125 inline bool Pred_t2_so_imm(SDNode *inN) const {
126 ConstantSDNode *N = cast(inN);
127 return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1;
128 }
119129
120130 // Include the pieces autogenerated from the target description.
121131 #include "ARMGenDAGISel.inc"
16851695 if (!T)
16861696 return 0;
16871697
1688 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1698 if (Pred_t2_so_imm(TrueVal.getNode())) {
16891699 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
16901700 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
16911701 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
17021712 if (!T)
17031713 return 0;
17041714
1705 if (Predicate_so_imm(TrueVal.getNode())) {
1715 if (Pred_so_imm(TrueVal.getNode())) {
17061716 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
17071717 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
17081718 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
17501760 }
17511761
17521762 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1753 // (imm:i32)<icate_so_imm>>:$true,
1763 // (imm:i32)<_so_imm>>:$true,
17541764 // (imm:i32):$cc)
17551765 // Emits: (MOVCCi:i32 GPR:i32:$false,
17561766 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
315315 // represented in the imm field in the same 12-bit form that they are encoded
316316 // into so_imm instructions: the 8-bit immediate is the least significant bits
317317 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
318 def so_imm : Operand,
319 PatLeaf<(imm), [{
320 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
321 }]> {
318 def so_imm : Operand, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
322319 let PrintMethod = "printSOImmOperand";
323320 }
324321
5050 // represented in the imm field in the same 12-bit form that they are encoded
5151 // into t2_so_imm instructions: the 8-bit immediate is the least significant
5252 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
53 def t2_so_imm : Operand,
54 PatLeaf<(imm), [{
55 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
56 }]>;
53 def t2_so_imm : Operand, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]>;
5754
5855 // t2_so_imm_not - Match an immediate that is a complement
5956 // of a t2_so_imm.