llvm.org GIT mirror llvm / 00ad914
[mips] Honour -mno-odd-spreg for vector splat Previous the lowering of FILL_FW would use the MSA128W register class when performing a vector splat. Instead it should be honouring -mno-odd-spreg and only use the even registers when performing a splat from word to vector register. Logical follow-on from r230235. This fixes PR/31369. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D28373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291556 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
2 changed file(s) with 18 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "MCTargetDesc/MipsABIInfo.h"
1314 #include "MipsTargetStreamer.h"
1415 #include "InstPrinter/MipsInstPrinter.h"
1516 #include "MipsELFStreamer.h"
683684 // the ABI, but this is fraught with wide ranging dependency
684685 // issues as well.
685686 unsigned EFlags = MCA.getELFHeaderEFlags();
687
688 // FIXME: Fix a dependency issue by instantiating the ABI object to some
689 // default based off the triple. The triple doesn't describe the target
690 // fully, but any external user of the API that uses the MCTargetStreamer
691 // would otherwise crash on assertion failure.
692
693 ABI = MipsABIInfo(
694 STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
695 STI.getTargetTriple().getArch() == Triple::ArchType::mips
696 ? MipsABIInfo::O32()
697 : MipsABIInfo::N64());
686698
687699 // Architecture
688700 if (Features[Mips::FeatureMips64r6])
33763376 DebugLoc DL = MI.getDebugLoc();
33773377 unsigned Wd = MI.getOperand(0).getReg();
33783378 unsigned Fs = MI.getOperand(1).getReg();
3379 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3380 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3379 unsigned Wt1 = RegInfo.createVirtualRegister(
3380 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3381 : &Mips::MSA128WEvensRegClass);
3382 unsigned Wt2 = RegInfo.createVirtualRegister(
3383 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3384 : &Mips::MSA128WEvensRegClass);
33813385
33823386 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
33833387 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)