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Convert tabs to spaces git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21438 91177308-0d34-0410-b5e6-96231b3b80d8 Misha Brukman 15 years ago
9 changed file(s) with 145 addition(s) and 148 deletion(s). Raw diff Collapse all Expand all
242242
243243 void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
244244 void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
245 MachineInstr *MI);
245 MachineInstr *MI);
246246 };
247247
248248 } // End llvm namespace
6060 void removeNodeFromList(MachineBasicBlock* N);
6161 void transferNodesFromList(iplist
6262 ilist_traits > &toList,
63 ilist_iterator first,
64 ilist_iterator last);
63 ilist_iterator first,
64 ilist_iterator last);
6565 };
6666
6767 /// MachineFunctionInfo - This class can be derived from and used by targets to
4242 // first and initialize each one later.
4343 //
4444 // E.g, for this VM instruction:
45 // ptr = alloca type, numElements
45 // ptr = alloca type, numElements
4646 // we generate 2 machine instructions on the SPARC:
4747 //
48 // mul Constant, Numelements -> Reg
49 // add %sp, Reg -> Ptr
48 // mul Constant, Numelements -> Reg
49 // add %sp, Reg -> Ptr
5050 //
5151 // Each instruction has 3 operands, listed above. Of those:
52 // - Reg, NumElements, and Ptr are of operand type MO_Register.
53 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
54 //
52 // - Reg, NumElements, and Ptr are of operand type MO_Register.
53 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
54 //
5555 // For the register operands, the virtual register type is as follows:
56 //
57 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
58 // MachineInstr* minstr will point to the instruction that computes reg.
59 //
60 // - %sp will be of virtual register type MO_MachineReg.
61 // The field regNum identifies the machine register.
62 //
63 // - NumElements will be of virtual register type MO_VirtualReg.
64 // The field Value* value identifies the value.
65 //
66 // - Ptr will also be of virtual register type MO_VirtualReg.
67 // Again, the field Value* value identifies the value.
56 //
57 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
58 // MachineInstr* minstr will point to the instruction that computes reg.
59 //
60 // - %sp will be of virtual register type MO_MachineReg.
61 // The field regNum identifies the machine register.
62 //
63 // - NumElements will be of virtual register type MO_VirtualReg.
64 // The field Value* value identifies the value.
65 //
66 // - Ptr will also be of virtual register type MO_VirtualReg.
67 // Again, the field Value* value identifies the value.
6868 //
6969 //===----------------------------------------------------------------------===//
7070
9595 };
9696
9797 enum MachineOperandType {
98 MO_VirtualRegister, // virtual register for *value
99 MO_MachineRegister, // pre-assigned machine register `regNum'
98 MO_VirtualRegister, // virtual register for *value
99 MO_MachineRegister, // pre-assigned machine register `regNum'
100100 MO_CCRegister,
101101 MO_SignExtendedImmed,
102102 MO_UnextendedImmed,
117117 // the generated machine code.
118118 // LLVM global for MO_GlobalAddress.
119119
120 int64_t immedVal; // Constant value for an explicit constant
120 int64_t immedVal; // Constant value for an explicit constant
121121
122122 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
123123 const char *SymbolName; // For MO_ExternalSymbol type
126126 char flags; // see bit field definitions above
127127 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
128128 union {
129 int regNum; // register number for an explicit register
129 int regNum; // register number for an explicit register
130130 // will be set for a value after reg allocation
131131
132132 int offset; // Offset to address of global or external, only
153153 }
154154
155155 MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
156 bool isPCRelative = false)
156 bool isPCRelative = false)
157157 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
158158 assert(OpTy != MachineOperand::MO_GlobalAddress);
159159 zeroContents();
162162 }
163163
164164 MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
165 bool isPCRelative = false, int Offset = 0)
165 bool isPCRelative = false, int Offset = 0)
166166 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
167167 assert(OpTy == MachineOperand::MO_GlobalAddress);
168168 zeroContents ();
365365 ///
366366 void setRegForValue(int reg) {
367367 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
368 opType == MO_MachineRegister);
368 opType == MO_MachineRegister);
369369 extra.regNum = reg;
370370 }
371371
5656
5757 // Iterators
5858 iterator beginInEdges() { return inEdges.begin(); }
59 iterator endInEdges() { return inEdges.end(); }
59 iterator endInEdges() { return inEdges.end(); }
6060 iterator beginOutEdges() { return outEdges.begin(); }
6161 iterator endOutEdges() { return outEdges.end(); }
6262
7272
7373 protected:
7474 friend class SchedGraphCommon;
75 friend class SchedGraphEdge; // give access for adding edges
75 friend class SchedGraphEdge; // give access for adding edges
7676
7777
7878 // disable default constructor and provide a ctor for single-block graphs
79 SchedGraphNodeCommon(); // DO NOT IMPLEMENT
79 SchedGraphNodeCommon(); // DO NOT IMPLEMENT
8080
8181 inline SchedGraphNodeCommon(unsigned Id, int index, int late=0) : ID(Id), latency(late), origIndexInBB(index) {}
8282
9292
9393 // ostream << operator for SchedGraphNode class
9494 inline std::ostream &operator<<(std::ostream &os,
95 const SchedGraphNodeCommon &node) {
95 const SchedGraphNodeCommon &node) {
9696 node.print(os);
9797 return os;
9898 }
113113 };
114114
115115 protected:
116 SchedGraphNodeCommon* src;
117 SchedGraphNodeCommon* sink;
116 SchedGraphNodeCommon* src;
117 SchedGraphNodeCommon* sink;
118118 SchedGraphEdgeDepType depType;
119119 unsigned int depOrderType;
120120 int minDelay; // cached latency (assumes fixed target arch)
126126 ResourceId resourceId;
127127 };
128128
129 public:
129 public:
130130 // For all constructors, if minDelay is unspecified, minDelay is
131131 // set to _src->getLatency().
132132
133133 // constructor for CtrlDep or MemoryDep edges, selected by 3rd argument
134134 SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink,
135 SchedGraphEdgeDepType _depType, unsigned int _depOrderType,
136 int _minDelay = -1);
135 SchedGraphEdgeDepType _depType, unsigned int _depOrderType,
136 int _minDelay = -1);
137137
138138 // constructor for explicit value dependence (may be true/anti/output)
139139 SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink,
140 const Value* _val, unsigned int _depOrderType,
141 int _minDelay = -1);
140 const Value* _val, unsigned int _depOrderType,
141 int _minDelay = -1);
142142
143143 // constructor for machine register dependence
144144 SchedGraphEdge(SchedGraphNodeCommon* _src,SchedGraphNodeCommon* _sink,
145 unsigned int _regNum, unsigned int _depOrderType,
146 int _minDelay = -1);
145 unsigned int _regNum, unsigned int _depOrderType,
146 int _minDelay = -1);
147147
148148 // constructor for any other machine resource dependences.
149149 // DataDepOrderType is always NonDataDep. It it not an argument to
150150 // avoid overloading ambiguity with previous constructor.
151151 SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink,
152 ResourceId _resourceId, int _minDelay = -1);
152 ResourceId _resourceId, int _minDelay = -1);
153153
154154 ~SchedGraphEdge() {}
155155
156 SchedGraphNodeCommon* getSrc() const { return src; }
157 SchedGraphNodeCommon* getSink() const { return sink; }
156 SchedGraphNodeCommon* getSrc() const { return src; }
157 SchedGraphNodeCommon* getSink() const { return sink; }
158158 int getMinDelay() const { return minDelay; }
159159 SchedGraphEdgeDepType getDepType() const { return depType; }
160160 unsigned int getDepOrderType() const { return depOrderType; }
186186
187187 private:
188188 // disable default ctor
189 SchedGraphEdge(); // DO NOT IMPLEMENT
189 SchedGraphEdge(); // DO NOT IMPLEMENT
190190 };
191191
192192 // ostream << operator for SchedGraphNode class
246246 inline _EdgeType* getEdge() const { return *(oi); }
247247
248248 inline _Self &operator++() { ++oi; return *this; } // Preincrement
249 inline _Self operator++(int) { // Postincrement
249 inline _Self operator++(int) { // Postincrement
250250 _Self tmp(*this); ++*this; return tmp;
251251 }
252252
253253 inline _Self &operator--() { --oi; return *this; } // Predecrement
254 inline _Self operator--(int) { // Postdecrement
254 inline _Self operator--(int) { // Postdecrement
255255 _Self tmp = *this; --*this; return tmp;
256256 }
257257 };
274274 inline _EdgeType* getEdge() const { return *(oi); }
275275
276276 inline _Self &operator++() { ++oi; return *this; } // Preincrement
277 inline _Self operator++(int) { // Postincrement
277 inline _Self operator++(int) { // Postincrement
278278 _Self tmp(*this); ++*this; return tmp;
279279 }
280280
281281 inline _Self &operator--() { --oi; return *this; } // Predecrement
282 inline _Self operator--(int) { // Postdecrement
282 inline _Self operator--(int) { // Postdecrement
283283 _Self tmp = *this; --*this; return tmp;
284284 }
285285 };
66 ******************************************************************************
77 *
88 * Description:
9 * This header file includes the infamous alloc.h header file if the
10 * autoconf system has found it. It hides all of the autoconf details
11 * from the rest of the application source code.
9 * This header file includes the infamous alloc.h header file if the
10 * autoconf system has found it. It hides all of the autoconf details
11 * from the rest of the application source code.
1212 */
1313
1414 #ifndef _CONFIG_ALLOC_H
1818
1919 /*
2020 * This is a modified version of that suggested by the Autoconf manual.
21 * 1) The #pragma is indented so that pre-ANSI C compilers ignore it.
22 * 2) If alloca.h cannot be found, then try stdlib.h. Some platforms
23 * (notably FreeBSD) defined alloca() there.
21 * 1) The #pragma is indented so that pre-ANSI C compilers ignore it.
22 * 2) If alloca.h cannot be found, then try stdlib.h. Some platforms
23 * (notably FreeBSD) defined alloca() there.
2424 */
2525 #ifdef _MSC_VER
2626 #include
3030 #elif defined(__MINGW32__) && defined(HAVE_MALLOC_H)
3131 #include
3232 #elif !defined(__GNUC__)
33 # ifdef _AIX
34 # pragma alloca
35 # else
36 # ifndef alloca
37 char * alloca ();
38 # endif
39 # endif
33 # ifdef _AIX
34 # pragma alloca
35 # else
36 # ifndef alloca
37 char * alloca ();
38 # endif
39 # endif
4040 #else
41 # ifdef HAVE_STDLIB_H
42 # include
43 # else
44 # error "The function alloca() is required but not found!"
45 # endif
41 # ifdef HAVE_STDLIB_H
42 # include
43 # else
44 # error "The function alloca() is required but not found!"
45 # endif
4646 #endif
4747
4848 #endif
122122 protected:
123123 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
124124 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
125 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
125 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
126126 virtual ~MRegisterInfo();
127127 public:
128128
284284 MachineBasicBlock &MBB,
285285 MachineBasicBlock::iterator MI) const {
286286 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
287 "eliminateCallFramePseudoInstr must be implemented if using"
288 " call frame setup/destroy pseudo instructions!");
287 "eliminateCallFramePseudoInstr must be implemented if using"
288 " call frame setup/destroy pseudo instructions!");
289289 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
290290 }
291291
8080
8181 // This method adjusts a stack offset to meet alignment rules of target.
8282 virtual int adjustAlignment(int unalignedOffset, bool growUp,
83 unsigned align) const;
83 unsigned align) const;
8484
8585 // These methods compute offsets using the frame contents for a particular
8686 // function. The frame contents are obtained from the MachineFunction object
8787 // for the given function. The rest must be implemented by the
8888 // machine-specific subclass.
8989 //
90 virtual int getIncomingArgOffset (MachineFunction& mcInfo,
91 unsigned argNum) const;
92 virtual int getOutgoingArgOffset (MachineFunction& mcInfo,
93 unsigned argNum) const;
94
95 virtual int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
96 bool& growUp) const;
97 virtual int getRegSpillAreaOffset (MachineFunction& mcInfo,
98 bool& growUp) const;
99 virtual int getTmpAreaOffset (MachineFunction& mcInfo,
100 bool& growUp) const;
101 virtual int getDynamicAreaOffset (MachineFunction& mcInfo,
102 bool& growUp) const;
90 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
91 unsigned argNum) const;
92 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
93 unsigned argNum) const;
94 virtual int getFirstAutomaticVarOffset(MachineFunction& mcInfo,
95 bool& growUp) const;
96 virtual int getRegSpillAreaOffset(MachineFunction& mcInfo,
97 bool& growUp) const;
98 virtual int getTmpAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
99 virtual int getDynamicAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
103100 };
104101
105102 } // End llvm namespace
3838
3939 //---------------------------------------------------------------------------
4040 // struct TargetInstrDescriptor:
41 // Predefined information about each machine instruction.
42 // Designed to initialized statically.
43 //
44
45 const unsigned M_NOP_FLAG = 1 << 0;
46 const unsigned M_BRANCH_FLAG = 1 << 1;
47 const unsigned M_CALL_FLAG = 1 << 2;
48 const unsigned M_RET_FLAG = 1 << 3;
49 const unsigned M_BARRIER_FLAG = 1 << 4;
50 const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
51 const unsigned M_CC_FLAG = 1 << 6;
52 const unsigned M_LOAD_FLAG = 1 << 7;
53 const unsigned M_STORE_FLAG = 1 << 8;
41 // Predefined information about each machine instruction.
42 // Designed to initialized statically.
43 //
44
45 const unsigned M_NOP_FLAG = 1 << 0;
46 const unsigned M_BRANCH_FLAG = 1 << 1;
47 const unsigned M_CALL_FLAG = 1 << 2;
48 const unsigned M_RET_FLAG = 1 << 3;
49 const unsigned M_BARRIER_FLAG = 1 << 4;
50 const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
51 const unsigned M_CC_FLAG = 1 << 6;
52 const unsigned M_LOAD_FLAG = 1 << 7;
53 const unsigned M_STORE_FLAG = 1 << 8;
5454
5555 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
56 const unsigned M_2_ADDR_FLAG = 1 << 9;
56 const unsigned M_2_ADDR_FLAG = 1 << 9;
5757
5858 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
5959 // changed into a 3-address instruction if the first two operands cannot be
7777 int numOperands; // Number of args; -1 if variable #args
7878 int resultPos; // Position of the result; -1 if no result
7979 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
80 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
80 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
8181 // smallest -ve value is -(maxImmedConst+1).
8282 unsigned numDelaySlots; // Number of delay slots after instruction
8383 unsigned latency; // Latency in machine cycles
274274 // of this machine instruction
275275 //
276276 virtual bool constantFitsInImmedField(MachineOpCode Opcode,
277 int64_t intValue) const;
277 int64_t intValue) const;
278278
279279 // Return the largest positive constant that can be held in the IMMED field
280280 // of this machine instruction.
283283 // Return 0 if the instruction has no IMMED field.
284284 //
285285 virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
286 bool &isSignExtended) const {
286 bool &isSignExtended) const {
287287 isSignExtended = get(Opcode).immedIsSignExtended;
288288 return get(Opcode).maxImmedConst;
289289 }
7171
7272 struct InstrClassRUsage {
7373 InstrSchedClass schedClass;
74 int totCycles;
74 int totCycles;
7575
7676 // Issue restrictions common to instructions in this class
7777 unsigned maxNumIssue;
78 bool isSingleIssue;
79 bool breaksGroup;
80 CycleCount_t numBubbles;
78 bool isSingleIssue;
79 bool breaksGroup;
80 CycleCount_t numBubbles;
8181
8282 // Feasible slots to use for instructions in this class.
8383 // The size of vector S[] is `numSlots'.
9090 struct {
9191 resourceId_t resourceId;
9292 unsigned startCycle;
93 int numCycles;
93 int numCycles;
9494 } V[MAX_NUM_CYCLES];
9595 };
9696
9797 struct InstrRUsageDelta {
9898 MachineOpCode opCode;
99 resourceId_t resourceId;
99 resourceId_t resourceId;
100100 unsigned startCycle;
101 int numCycles;
101 int numCycles;
102102 };
103103
104104 // Specify instruction issue restrictions for individual instructions
105105 // that differ from the common rules for the class.
106106 //
107107 struct InstrIssueDelta {
108 MachineOpCode opCode;
109 bool isSingleIssue;
110 bool breaksGroup;
111 CycleCount_t numBubbles;
108 MachineOpCode opCode;
109 bool isSingleIssue;
110 bool breaksGroup;
111 CycleCount_t numBubbles;
112112 };
113113
114114
115115 struct InstrRUsage {
116 bool sameAsClass;
116 bool sameAsClass;
117117
118118 // Issue restrictions for this instruction
119 bool isSingleIssue;
120 bool breaksGroup;
121 CycleCount_t numBubbles;
119 bool isSingleIssue;
120 bool breaksGroup;
121 CycleCount_t numBubbles;
122122
123123 // Feasible slots to use for this instruction.
124124 std::vector feasibleSlots;
125125
126126 // Resource usages for this instruction, with one resource vector per cycle.
127 CycleCount_t numCycles;
127 CycleCount_t numCycles;
128128 std::vector > resourcesByCycle;
129129
130130 private:
138138 numBubbles = delta.numBubbles;
139139 }
140140
141 void addUsageDelta (const InstrRUsageDelta& delta);
142 void setMaxSlots (int maxNumSlots) {
141 void addUsageDelta(const InstrRUsageDelta& delta);
142 void setMaxSlots(int maxNumSlots) {
143143 feasibleSlots.resize(maxNumSlots);
144144 }
145145
146 friend class TargetSchedInfo; // give access to these functions
146 friend class TargetSchedInfo; // give access to these functions
147147 };
148148
149149
156156 const TargetMachine& target;
157157
158158 unsigned maxNumIssueTotal;
159 int longestIssueConflict;
159 int longestIssueConflict;
160160
161161 protected:
162162 inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
172172 TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT
173173 void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT
174174 public:
175 /*ctor*/ TargetSchedInfo (const TargetMachine& tgt,
176 int _numSchedClasses,
177 const InstrClassRUsage* _classRUsages,
178 const InstrRUsageDelta* _usageDeltas,
179 const InstrIssueDelta* _issueDeltas,
180 unsigned _numUsageDeltas,
181 unsigned _numIssueDeltas);
182 /*dtor*/ virtual ~TargetSchedInfo() {}
175 TargetSchedInfo(const TargetMachine& tgt,
176 int _numSchedClasses,
177 const InstrClassRUsage* _classRUsages,
178 const InstrRUsageDelta* _usageDeltas,
179 const InstrIssueDelta* _issueDeltas,
180 unsigned _numUsageDeltas,
181 unsigned _numIssueDeltas);
182 virtual ~TargetSchedInfo() {}
183183
184184 inline const TargetInstrInfo& getInstrInfo() const {
185185 return *mii;
186186 }
187187
188 inline int getNumSchedClasses() const {
188 inline int getNumSchedClasses() const {
189189 return numSchedClasses;
190190 }
191191
198198 return classRUsages[sc].maxNumIssue;
199199 }
200200
201 inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
201 inline InstrSchedClass getSchedClass(MachineOpCode opCode) const {
202202 return getInstrInfo().getSchedClass(opCode);
203203 }
204204
205 inline bool instrCanUseSlot (MachineOpCode opCode,
206 unsigned s) const {
205 inline bool instrCanUseSlot(MachineOpCode opCode,
206 unsigned s) const {
207207 assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
208208 return getInstrRUsage(opCode).feasibleSlots[s];
209209 }
210210
211 inline int getLongestIssueConflict () const {
211 inline int getLongestIssueConflict() const {
212212 return longestIssueConflict;
213213 }
214214
215 inline int getMinIssueGap (MachineOpCode fromOp,
216 MachineOpCode toOp) const {
215 inline int getMinIssueGap(MachineOpCode fromOp,
216 MachineOpCode toOp) const {
217217 assert(fromOp < (int) issueGaps.size());
218218 const std::vector& toGaps = issueGaps[fromOp];
219219 return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
220220 }
221221
222222 inline const std::vector&
223 getConflictList(MachineOpCode opCode) const {
223 getConflictList(MachineOpCode opCode) const {
224224 assert(opCode < (int) conflictLists.size());
225225 return conflictLists[opCode];
226226 }
227227
228 inline bool isSingleIssue (MachineOpCode opCode) const {
228 inline bool isSingleIssue(MachineOpCode opCode) const {
229229 return getInstrRUsage(opCode).isSingleIssue;
230230 }
231231
232 inline bool breaksIssueGroup (MachineOpCode opCode) const {
232 inline bool breaksIssueGroup(MachineOpCode opCode) const {
233233 return getInstrRUsage(opCode).breaksGroup;
234234 }
235235
236 inline unsigned numBubblesAfter (MachineOpCode opCode) const {
236 inline unsigned numBubblesAfter(MachineOpCode opCode) const {
237237 return getInstrRUsage(opCode).numBubbles;
238238 }
239239
247247
248248
249249 protected:
250 virtual void initializeResources ();
250 virtual void initializeResources();
251251
252252 private:
253253 void computeInstrResources(const std::vector& instrRUForClasses);
264264 std::vector > resourceNumVector;
265265
266266 protected:
267 unsigned numSchedClasses;
267 unsigned numSchedClasses;
268268 const TargetInstrInfo* mii;
269 const InstrClassRUsage* classRUsages; // raw array by sclass
270 const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
271 const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
272 unsigned numUsageDeltas;
273 unsigned numIssueDeltas;
269 const InstrClassRUsage* classRUsages; // raw array by sclass
270 const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
271 const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
272 unsigned numUsageDeltas;
273 unsigned numIssueDeltas;
274274
275275 std::vector instrRUsages; // indexed by opcode
276276 std::vector > issueGaps; // indexed by [opcode1][opcode2]
277277 std::vector >
278 conflictLists; // indexed by [opcode]
278 conflictLists; // indexed by [opcode]
279279
280280
281281 friend class ModuloSchedulingPass;