llvm.org GIT mirror llvm / 0048957
[ARM] Add command-line option for SB SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also renames FeatureSpecRestrict to FeatureSB. Reviewed By: olista01, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55990 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350299 91177308-0d34-0410-b5e6-96231b3b80d8 Diogo N. Sampaio 8 months ago
15 changed file(s) with 48 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
157157 ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr)
158158 ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
159159 ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml")
160 ARM_ARCH_EXT_NAME("sb", ARM::AEK_SB, "+sb", "-sb")
160161 #undef ARM_ARCH_EXT_NAME
161162
162163 #ifndef ARM_HW_DIV_NAME
4444 AEK_SHA2 = 1 << 15,
4545 AEK_AES = 1 << 16,
4646 AEK_FP16FML = 1 << 17,
47 AEK_SB = 1 << 18,
4748 // Unsupported extensions.
4849 AEK_OS = 0x8000000,
4950 AEK_IWMMXT = 0x10000000,
364364
365365 // Armv8.5-A extensions
366366
367 def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
368 "Enable speculation control barrier" >;
367 def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
368 "Enable v8.5a Speculation Barrier" >;
369369
370370 //===----------------------------------------------------------------------===//
371371 // ARM architecture class
458458
459459 def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
460460 "Support ARM v8.5a instructions",
461 [HasV8_4aOps, FeatureSpecCtrl]>;
461 [HasV8_4aOps, FeatureSB]>;
462462
463463 //===----------------------------------------------------------------------===//
464464 // ARM Processor subtarget features.
394394 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
395395
396396 // Armv8.5-A extensions
397 def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
398 AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
397 def HasSB : Predicate<"Subtarget->hasSB()">,
398 AssemblerPredicate<"FeatureSB", "sb">;
399399
400400 //===----------------------------------------------------------------------===//
401401 // ARM Flag Definitions.
48944894
48954895 // Armv8.5-A speculation barrier
48964896 def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>,
4897 Requires<[IsARM, HasSpecCtrl]>, Sched<[]> {
4897 Requires<[IsARM, HasSB]>, Sched<[]> {
48984898 let Inst{31-0} = 0xf57ff070;
48994899 let Unpredictable = 0x000fff0f;
49004900 let hasSideEffects = 1;
32383238
32393239 // Armv8.5-A speculation barrier
32403240 def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
3241 Requires<[IsThumb2, HasSpecCtrl]>, Sched<[]> {
3241 Requires<[IsThumb2, HasSB]>, Sched<[]> {
32423242 let Inst{31-0} = 0xf3bf8f70;
32433243 let Unpredictable = 0x000f2f0f;
32443244 let hasSideEffects = 1;
416416 bool UseSjLjEH = false;
417417
418418 /// Has speculation barrier
419 bool HasSpecCtrl = false;
419 bool HasSB = false;
420420
421421 /// Implicitly convert an instruction to a different one if its immediates
422422 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
627627 bool hasDSP() const { return HasDSP; }
628628 bool useNaClTrap() const { return UseNaClTrap; }
629629 bool useSjLjEH() const { return UseSjLjEH; }
630 bool hasSpecCtrl() const { return HasSpecCtrl; }
630 bool hasSB() const { return HasSB; }
631631 bool genLongCalls() const { return GenLongCalls; }
632632 bool genExecuteOnly() const { return GenExecuteOnly; }
633633
0 // RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s 2>&1 | FileCheck %s
1
2 it eq
3 sbeq
4
5 // CHECK: instruction 'sb' is not predicable, but condition code specified
0 // RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s 2>&1 | FileCheck %s
1
2 sbeq
3
4 // CHECK: instruction 'sb' is not predicable
0 // RUN: llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s | FileCheck %s
1 // RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
2 // RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3 // RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s | FileCheck %s --check-prefix=THUMB
4 // RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
5 // RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
6
7 // Flag manipulation
8 sb
9
10 // CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
11 // THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
12
13 // NOSB: instruction requires: sb
14 // NOSB-NEXT: sb
+0
-6
test/MC/ARM/armv8.5a-specctrl-error-thumb.s less more
None // RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
1
2 it eq
3 sbeq
4
5 // CHECK: instruction 'sb' is not predicable, but condition code specified
+0
-5
test/MC/ARM/armv8.5a-specctrl-error.s less more
None // RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
1
2 sbeq
3
4 // CHECK: instruction 'sb' is not predicable
+0
-15
test/MC/ARM/armv8.5a-specctrl.s less more
None // RUN: llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s
1 // RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
2 // RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3 // RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s --check-prefix=THUMB
4 // RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
5 // RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
6
7 // Flag manipulation
8 sb
9
10 // CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
11 // THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
12
13 // NOSB: instruction requires: specctrl
14 // NOSB-NEXT: sb
0 # RUN: llvm-mc -triple=thumbv8 -mattr=+sb -disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=thumbv8 -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 0xbf 0xf3 0x70 0x8f
5
6 # CHECK: sb
7 # NOSB: invalid instruction encoding
8 # NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
+0
-9
test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt less more
None # RUN: llvm-mc -triple=thumbv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=thumbv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 0xbf 0xf3 0x70 0x8f
5
6 # CHECK: sb
7 # NOSB: invalid instruction encoding
8 # NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
583583 {"iwmmxt", "noiwmmxt", nullptr, nullptr},
584584 {"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
585585 {"maverick", "maverick", nullptr, nullptr},
586 {"xscale", "noxscale", nullptr, nullptr}};
586 {"xscale", "noxscale", nullptr, nullptr},
587 {"sb", "nosb", "+sb", "-sb"}};
587588
588589 for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
589590 EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));