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ARM: fix WoA PEI instruction selection The ARM::BLX instruction is an ARM mode instruction. The Windows on ARM target is limited to Thumb instructions. Correctly use the thumb mode tBLXr instruction. This would manifest as an errant write into the object file as the instruction is 4-bytes in length rather than 2. The result would be a corrupted object file that would eventually result in an executable that would crash at runtime. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208152 91177308-0d34-0410-b5e6-96231b3b80d8 Saleem Abdulrasool 6 years ago
2 changed file(s) with 29 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
318318 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
319319 .addExternalSymbol("__chkstk");
320320
321 BuildMI(MBB, MBBI, dl, TII.get(ARM::BLX))
321 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
322 .addImm((unsigned)ARMCC::AL).addReg(0)
322323 .addReg(ARM::R12, RegState::Kill)
323324 .addReg(ARM::R4, RegState::Implicit);
324325 break;
0 ; RUN: llc -mtriple thumbv7--windows-itanium -code-model large -filetype obj -o - %s \
1 ; RUN: | llvm-objdump -no-show-raw-insn -d - | FileCheck %s
2
3 ; ModuleID = 'reduced.c'
4 target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
5 target triple = "thumbv7--windows-itanium"
6
7 define arm_aapcs_vfpcc i8 @isel(i32 %i) {
8 entry:
9 %i.addr = alloca i32, align 4
10 %buffer = alloca [4096 x i8], align 1
11 store i32 %i, i32* %i.addr, align 4
12 %0 = load i32* %i.addr, align 4
13 %rem = urem i32 %0, 4096
14 %arrayidx = getelementptr inbounds [4096 x i8]* %buffer, i32 0, i32 %rem
15 %1 = load volatile i8* %arrayidx, align 1
16 ret i8 %1
17 }
18
19 ; CHECK-LABEL: isel
20 ; CHECK: push {r4, r5}
21 ; CHECK: movw r4, #{{\d*}}
22 ; CHECK: movw r12, #0
23 ; CHECK: movt r12, #0
24 ; CHECK: blx r12
25 ; CHECK: sub.w sp, sp, r4
26