llvm.org GIT mirror llvm / 0020723
Add fast register allocator, enabled with -regalloc=fast. So far this is just a clone of -regalloc=local that has been lobotomized to run 25% faster. It drops the least-recently-used calculations, and is just plain stupid when it runs out of registers. The plan is to make this go even faster for -O0 by taking advantage of the short live intervals in unoptimized code. It should not be necessary to calculate liveness when most virtual registers are killed 2-3 instructions after they are born. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102006 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
4 changed file(s) with 1114 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
3333 (void) llvm::createDeadMachineInstructionElimPass();
3434
3535 (void) llvm::createLocalRegisterAllocator();
36 (void) llvm::createFastRegisterAllocator();
3637 (void) llvm::createLinearScanRegisterAllocator();
3738 (void) llvm::createPBQPRegisterAllocator();
3839
9494 ///
9595 FunctionPass *createLocalRegisterAllocator();
9696
97 /// FastRegisterAllocation Pass - This pass register allocates as fast as
98 /// possible. It is best suited for debug code where live ranges are short.
99 ///
100 FunctionPass *createFastRegisterAllocator();
101
97102 /// LinearScanRegisterAllocation Pass - This pass implements the linear scan
98103 /// register allocation algorithm, a global register allocator.
99104 ///
4949 ProcessImplicitDefs.cpp
5050 PrologEpilogInserter.cpp
5151 PseudoSourceValue.cpp
52 RegAllocFast.cpp
5253 RegAllocLinearScan.cpp
5354 RegAllocLocal.cpp
5455 RegAllocPBQP.cpp
0 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This register allocator allocates registers to a basic block at a time,
10 // attempting to keep values in registers and reusing registers as appropriate.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "regalloc"
15 #include "llvm/BasicBlock.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/RegAllocRegistry.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/IndexedMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include
35 using namespace llvm;
36
37 STATISTIC(NumStores, "Number of stores added");
38 STATISTIC(NumLoads , "Number of loads added");
39
40 static RegisterRegAlloc
41 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
42
43 namespace {
44 class RAFast : public MachineFunctionPass {
45 public:
46 static char ID;
47 RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
48 private:
49 const TargetMachine *TM;
50 MachineFunction *MF;
51 const TargetRegisterInfo *TRI;
52 const TargetInstrInfo *TII;
53
54 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
55 // values are spilled.
56 IndexedMap StackSlotForVirtReg;
57
58 // Virt2PhysRegMap - This map contains entries for each virtual register
59 // that is currently available in a physical register.
60 IndexedMap Virt2PhysRegMap;
61
62 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
63 return Virt2PhysRegMap[VirtReg];
64 }
65
66 // PhysRegsUsed - This array is effectively a map, containing entries for
67 // each physical register that currently has a value (ie, it is in
68 // Virt2PhysRegMap). The value mapped to is the virtual register
69 // corresponding to the physical register (the inverse of the
70 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
71 // because it is used by a future instruction, and to -2 if it is not
72 // allocatable. If the entry for a physical register is -1, then the
73 // physical register is "not in the map".
74 //
75 std::vector PhysRegsUsed;
76
77 // UsedInInstr - BitVector of physregs that are used in the current
78 // instruction, and so cannot be allocated.
79 BitVector UsedInInstr;
80
81 // Virt2LastUseMap - This maps each virtual register to its last use
82 // (MachineInstr*, operand index pair).
83 IndexedMap, VirtReg2IndexFunctor>
84 Virt2LastUseMap;
85
86 std::pair& getVirtRegLastUse(unsigned Reg) {
87 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
88 return Virt2LastUseMap[Reg];
89 }
90
91 // VirtRegModified - This bitset contains information about which virtual
92 // registers need to be spilled back to memory when their registers are
93 // scavenged. If a virtual register has simply been rematerialized, there
94 // is no reason to spill it to memory when we need the register back.
95 //
96 BitVector VirtRegModified;
97
98 // UsedInMultipleBlocks - Tracks whether a particular register is used in
99 // more than one block.
100 BitVector UsedInMultipleBlocks;
101
102 void markVirtRegModified(unsigned Reg, bool Val = true) {
103 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
104 Reg -= TargetRegisterInfo::FirstVirtualRegister;
105 if (Val)
106 VirtRegModified.set(Reg);
107 else
108 VirtRegModified.reset(Reg);
109 }
110
111 bool isVirtRegModified(unsigned Reg) const {
112 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
113 assert(Reg - TargetRegisterInfo::FirstVirtualRegister <
114 VirtRegModified.size() && "Illegal virtual register!");
115 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
116 }
117
118 public:
119 virtual const char *getPassName() const {
120 return "Fast Register Allocator";
121 }
122
123 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
124 AU.setPreservesCFG();
125 AU.addRequiredID(PHIEliminationID);
126 AU.addRequiredID(TwoAddressInstructionPassID);
127 MachineFunctionPass::getAnalysisUsage(AU);
128 }
129
130 private:
131 /// runOnMachineFunction - Register allocate the whole function
132 bool runOnMachineFunction(MachineFunction &Fn);
133
134 /// AllocateBasicBlock - Register allocate the specified basic block.
135 void AllocateBasicBlock(MachineBasicBlock &MBB);
136
137
138 /// areRegsEqual - This method returns true if the specified registers are
139 /// related to each other. To do this, it checks to see if they are equal
140 /// or if the first register is in the alias set of the second register.
141 ///
142 bool areRegsEqual(unsigned R1, unsigned R2) const {
143 if (R1 == R2) return true;
144 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
145 *AliasSet; ++AliasSet) {
146 if (*AliasSet == R1) return true;
147 }
148 return false;
149 }
150
151 /// getStackSpaceFor - This returns the frame index of the specified virtual
152 /// register on the stack, allocating space if necessary.
153 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
154
155 /// removePhysReg - This method marks the specified physical register as no
156 /// longer being in use.
157 ///
158 void removePhysReg(unsigned PhysReg);
159
160 /// spillVirtReg - This method spills the value specified by PhysReg into
161 /// the virtual register slot specified by VirtReg. It then updates the RA
162 /// data structures to indicate the fact that PhysReg is now available.
163 ///
164 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
165 unsigned VirtReg, unsigned PhysReg);
166
167 /// spillPhysReg - This method spills the specified physical register into
168 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
169 /// true, then the request is ignored if the physical register does not
170 /// contain a virtual register.
171 ///
172 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
173 unsigned PhysReg, bool OnlyVirtRegs = false);
174
175 /// assignVirtToPhysReg - This method updates local state so that we know
176 /// that PhysReg is the proper container for VirtReg now. The physical
177 /// register must not be used for anything else when this is called.
178 ///
179 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
180
181 /// isPhysRegAvailable - Return true if the specified physical register is
182 /// free and available for use. This also includes checking to see if
183 /// aliased registers are all free...
184 ///
185 bool isPhysRegAvailable(unsigned PhysReg) const;
186
187 /// isPhysRegSpillable - Can PhysReg be freed by spilling?
188 bool isPhysRegSpillable(unsigned PhysReg) const;
189
190 /// getFreeReg - Look to see if there is a free register available in the
191 /// specified register class. If not, return 0.
192 ///
193 unsigned getFreeReg(const TargetRegisterClass *RC);
194
195 /// getReg - Find a physical register to hold the specified virtual
196 /// register. If all compatible physical registers are used, this method
197 /// spills the last used virtual register to the stack, and uses that
198 /// register. If NoFree is true, that means the caller knows there isn't
199 /// a free register, do not call getFreeReg().
200 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
201 unsigned VirtReg, bool NoFree = false);
202
203 /// reloadVirtReg - This method transforms the specified virtual
204 /// register use to refer to a physical register. This method may do this
205 /// in one of several ways: if the register is available in a physical
206 /// register already, it uses that physical register. If the value is not
207 /// in a physical register, and if there are physical registers available,
208 /// it loads it into a register: PhysReg if that is an available physical
209 /// register, otherwise any physical register of the right class.
210 /// If register pressure is high, and it is possible, it tries to fold the
211 /// load of the virtual register into the instruction itself. It avoids
212 /// doing this if register pressure is low to improve the chance that
213 /// subsequent instructions can use the reloaded value. This method
214 /// returns the modified instruction.
215 ///
216 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
217 unsigned OpNum, SmallSet &RRegs,
218 unsigned PhysReg);
219
220 /// ComputeLocalLiveness - Computes liveness of registers within a basic
221 /// block, setting the killed/dead flags as appropriate.
222 void ComputeLocalLiveness(MachineBasicBlock& MBB);
223
224 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
225 unsigned PhysReg);
226 };
227 char RAFast::ID = 0;
228 }
229
230 /// getStackSpaceFor - This allocates space for the specified virtual register
231 /// to be held on the stack.
232 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
233 // Find the location Reg would belong...
234 int SS = StackSlotForVirtReg[VirtReg];
235 if (SS != -1)
236 return SS; // Already has space allocated?
237
238 // Allocate a new stack object for this spill location...
239 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
240 RC->getAlignment());
241
242 // Assign the slot.
243 StackSlotForVirtReg[VirtReg] = FrameIdx;
244 return FrameIdx;
245 }
246
247
248 /// removePhysReg - This method marks the specified physical register as no
249 /// longer being in use.
250 ///
251 void RAFast::removePhysReg(unsigned PhysReg) {
252 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
253 }
254
255
256 /// spillVirtReg - This method spills the value specified by PhysReg into the
257 /// virtual register slot specified by VirtReg. It then updates the RA data
258 /// structures to indicate the fact that PhysReg is now available.
259 ///
260 void RAFast::spillVirtReg(MachineBasicBlock &MBB,
261 MachineBasicBlock::iterator I,
262 unsigned VirtReg, unsigned PhysReg) {
263 assert(VirtReg && "Spilling a physical register is illegal!"
264 " Must not have appropriate kill for the register or use exists beyond"
265 " the intended one.");
266 DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
267 << " containing %reg" << VirtReg);
268
269 if (!isVirtRegModified(VirtReg)) {
270 DEBUG(dbgs() << " which has not been modified, so no store necessary!");
271 std::pair &LastUse = getVirtRegLastUse(VirtReg);
272 if (LastUse.first)
273 LastUse.first->getOperand(LastUse.second).setIsKill();
274 } else {
275 // Otherwise, there is a virtual register corresponding to this physical
276 // register. We only need to spill it into its stack slot if it has been
277 // modified.
278 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
279 int FrameIndex = getStackSpaceFor(VirtReg, RC);
280 DEBUG(dbgs() << " to stack slot #" << FrameIndex);
281 // If the instruction reads the register that's spilled, (e.g. this can
282 // happen if it is a move to a physical register), then the spill
283 // instruction is not a kill.
284 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
285 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
286 ++NumStores; // Update statistics
287 }
288
289 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
290
291 DEBUG(dbgs() << '\n');
292 removePhysReg(PhysReg);
293 }
294
295
296 /// spillPhysReg - This method spills the specified physical register into the
297 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
298 /// then the request is ignored if the physical register does not contain a
299 /// virtual register.
300 ///
301 void RAFast::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
302 unsigned PhysReg, bool OnlyVirtRegs) {
303 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
304 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
305 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
306 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
307 return;
308 }
309
310 // If the selected register aliases any other registers, we must make
311 // sure that one of the aliases isn't alive.
312 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
313 *AliasSet; ++AliasSet) {
314 if (PhysRegsUsed[*AliasSet] == -1 || // Spill aliased register.
315 PhysRegsUsed[*AliasSet] == -2) // If allocatable.
316 continue;
317
318 if (PhysRegsUsed[*AliasSet])
319 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
320 }
321 }
322
323
324 /// assignVirtToPhysReg - This method updates local state so that we know
325 /// that PhysReg is the proper container for VirtReg now. The physical
326 /// register must not be used for anything else when this is called.
327 ///
328 void RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
329 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
330 // Update information to note the fact that this register was just used, and
331 // it holds VirtReg.
332 PhysRegsUsed[PhysReg] = VirtReg;
333 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
334 UsedInInstr.set(PhysReg);
335 }
336
337
338 /// isPhysRegAvailable - Return true if the specified physical register is free
339 /// and available for use. This also includes checking to see if aliased
340 /// registers are all free...
341 ///
342 bool RAFast::isPhysRegAvailable(unsigned PhysReg) const {
343 if (PhysRegsUsed[PhysReg] != -1) return false;
344
345 // If the selected register aliases any other allocated registers, it is
346 // not free!
347 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
348 *AliasSet; ++AliasSet)
349 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
350 return false; // Can't use this reg then.
351 return true;
352 }
353
354 /// isPhysRegSpillable - Return true if the specified physical register can be
355 /// spilled for use in the current instruction.
356 ///
357 bool RAFast::isPhysRegSpillable(unsigned PhysReg) const {
358 // Test that PhysReg and all aliases are either free or assigned to a VirtReg
359 // that is not used in the instruction.
360 if (PhysRegsUsed[PhysReg] != -1 &&
361 (PhysRegsUsed[PhysReg] <= 0 || UsedInInstr.test(PhysReg)))
362 return false;
363
364 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
365 *AliasSet; ++AliasSet)
366 if (PhysRegsUsed[*AliasSet] != -1 &&
367 (PhysRegsUsed[*AliasSet] <= 0 || UsedInInstr.test(*AliasSet)))
368 return false;
369 return true;
370 }
371
372
373 /// getFreeReg - Look to see if there is a free register available in the
374 /// specified register class. If not, return 0.
375 ///
376 unsigned RAFast::getFreeReg(const TargetRegisterClass *RC) {
377 // Get iterators defining the range of registers that are valid to allocate in
378 // this class, which also specifies the preferred allocation order.
379 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
380 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
381
382 for (; RI != RE; ++RI)
383 if (isPhysRegAvailable(*RI)) { // Is reg unused?
384 assert(*RI != 0 && "Cannot use register!");
385 return *RI; // Found an unused register!
386 }
387 return 0;
388 }
389
390
391 /// getReg - Find a physical register to hold the specified virtual
392 /// register. If all compatible physical registers are used, this method spills
393 /// the last used virtual register to the stack, and uses that register.
394 ///
395 unsigned RAFast::getReg(MachineBasicBlock &MBB, MachineInstr *I,
396 unsigned VirtReg, bool NoFree) {
397 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
398
399 // First check to see if we have a free register of the requested type...
400 unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
401
402 if (PhysReg != 0) {
403 // Assign the register.
404 assignVirtToPhysReg(VirtReg, PhysReg);
405 return PhysReg;
406 }
407
408 // If we didn't find an unused register, scavenge one now! Don't be fancy,
409 // just grab the first possible register.
410 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
411 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
412
413 for (; RI != RE; ++RI)
414 if (isPhysRegSpillable(*RI)) {
415 PhysReg = *RI;
416 break;
417 }
418
419 assert(PhysReg && "Physical register not assigned!?!?");
420 spillPhysReg(MBB, I, PhysReg);
421 assignVirtToPhysReg(VirtReg, PhysReg);
422 return PhysReg;
423 }
424
425
426 /// reloadVirtReg - This method transforms the specified virtual
427 /// register use to refer to a physical register. This method may do this in
428 /// one of several ways: if the register is available in a physical register
429 /// already, it uses that physical register. If the value is not in a physical
430 /// register, and if there are physical registers available, it loads it into a
431 /// register: PhysReg if that is an available physical register, otherwise any
432 /// register. If register pressure is high, and it is possible, it tries to
433 /// fold the load of the virtual register into the instruction itself. It
434 /// avoids doing this if register pressure is low to improve the chance that
435 /// subsequent instructions can use the reloaded value. This method returns
436 /// the modified instruction.
437 ///
438 MachineInstr *RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
439 unsigned OpNum,
440 SmallSet &ReloadedRegs,
441 unsigned PhysReg) {
442 unsigned VirtReg = MI->getOperand(OpNum).getReg();
443
444 // If the virtual register is already available, just update the instruction
445 // and return.
446 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
447 MI->getOperand(OpNum).setReg(PR); // Assign the input register
448 if (!MI->isDebugValue()) {
449 // Do not do these for DBG_VALUE as they can affect codegen.
450 UsedInInstr.set(PR);
451 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
452 }
453 return MI;
454 }
455
456 // Otherwise, we need to fold it into the current instruction, or reload it.
457 // If we have registers available to hold the value, use them.
458 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
459 // If we already have a PhysReg (this happens when the instruction is a
460 // reg-to-reg copy with a PhysReg destination) use that.
461 if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
462 !isPhysRegAvailable(PhysReg))
463 PhysReg = getFreeReg(RC);
464 int FrameIndex = getStackSpaceFor(VirtReg, RC);
465
466 if (PhysReg) { // Register is available, allocate it!
467 assignVirtToPhysReg(VirtReg, PhysReg);
468 } else { // No registers available.
469 // Force some poor hapless value out of the register file to
470 // make room for the new register, and reload it.
471 PhysReg = getReg(MBB, MI, VirtReg, true);
472 }
473
474 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
475
476 DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
477 << TRI->getName(PhysReg) << "\n");
478
479 // Add move instruction(s)
480 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
481 ++NumLoads; // Update statistics
482
483 MF->getRegInfo().setPhysRegUsed(PhysReg);
484 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
485 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
486
487 if (!ReloadedRegs.insert(PhysReg)) {
488 std::string msg;
489 raw_string_ostream Msg(msg);
490 Msg << "Ran out of registers during register allocation!";
491 if (MI->isInlineAsm()) {
492 Msg << "\nPlease check your inline asm statement for invalid "
493 << "constraints:\n";
494 MI->print(Msg, TM);
495 }
496 report_fatal_error(Msg.str());
497 }
498 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
499 *SubRegs; ++SubRegs) {
500 if (ReloadedRegs.insert(*SubRegs)) continue;
501
502 std::string msg;
503 raw_string_ostream Msg(msg);
504 Msg << "Ran out of registers during register allocation!";
505 if (MI->isInlineAsm()) {
506 Msg << "\nPlease check your inline asm statement for invalid "
507 << "constraints:\n";
508 MI->print(Msg, TM);
509 }
510 report_fatal_error(Msg.str());
511 }
512
513 return MI;
514 }
515
516 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
517 /// read/mod/write register, i.e. update partial register.
518 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
519 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
520 MachineOperand &MO = MI->getOperand(i);
521 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
522 MO.isDef() && !MO.isDead())
523 return true;
524 }
525 return false;
526 }
527
528 /// isReadModWriteImplicitDef - True if this is an implicit def for a
529 /// read/mod/write register, i.e. update partial register.
530 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
531 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
532 MachineOperand &MO = MI->getOperand(i);
533 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
534 !MO.isDef() && MO.isKill())
535 return true;
536 }
537 return false;
538 }
539
540 // precedes - Helper function to determine with MachineInstr A
541 // precedes MachineInstr B within the same MBB.
542 static bool precedes(MachineBasicBlock::iterator A,
543 MachineBasicBlock::iterator B) {
544 if (A == B)
545 return false;
546
547 MachineBasicBlock::iterator I = A->getParent()->begin();
548 while (I != A->getParent()->end()) {
549 if (I == A)
550 return true;
551 else if (I == B)
552 return false;
553
554 ++I;
555 }
556
557 return false;
558 }
559
560 /// ComputeLocalLiveness - Computes liveness of registers within a basic
561 /// block, setting the killed/dead flags as appropriate.
562 void RAFast::ComputeLocalLiveness(MachineBasicBlock& MBB) {
563 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
564 // Keep track of the most recently seen previous use or def of each reg,
565 // so that we can update them with dead/kill markers.
566 DenseMap > LastUseDef;
567 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
568 I != E; ++I) {
569 if (I->isDebugValue())
570 continue;
571
572 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
573 MachineOperand &MO = I->getOperand(i);
574 // Uses don't trigger any flags, but we need to save
575 // them for later. Also, we have to process these
576 // _before_ processing the defs, since an instr
577 // uses regs before it defs them.
578 if (!MO.isReg() || !MO.getReg() || !MO.isUse())
579 continue;
580
581 LastUseDef[MO.getReg()] = std::make_pair(I, i);
582
583 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
584
585 const unsigned *Aliases = TRI->getAliasSet(MO.getReg());
586 if (Aliases == 0)
587 continue;
588
589 while (*Aliases) {
590 DenseMap >::iterator
591 alias = LastUseDef.find(*Aliases);
592
593 if (alias != LastUseDef.end() && alias->second.first != I)
594 LastUseDef[*Aliases] = std::make_pair(I, i);
595
596 ++Aliases;
597 }
598 }
599
600 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
601 MachineOperand &MO = I->getOperand(i);
602 // Defs others than 2-addr redefs _do_ trigger flag changes:
603 // - A def followed by a def is dead
604 // - A use followed by a def is a kill
605 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue;
606
607 DenseMap >::iterator
608 last = LastUseDef.find(MO.getReg());
609 if (last != LastUseDef.end()) {
610 // Check if this is a two address instruction. If so, then
611 // the def does not kill the use.
612 if (last->second.first == I &&
613 I->isRegTiedToUseOperand(i))
614 continue;
615
616 MachineOperand &lastUD =
617 last->second.first->getOperand(last->second.second);
618 if (lastUD.isDef())
619 lastUD.setIsDead(true);
620 else
621 lastUD.setIsKill(true);
622 }
623
624 LastUseDef[MO.getReg()] = std::make_pair(I, i);
625 }
626 }
627
628 // Live-out (of the function) registers contain return values of the function,
629 // so we need to make sure they are alive at return time.
630 MachineBasicBlock::iterator Ret = MBB.getFirstTerminator();
631 bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn());
632
633 if (BBEndsInReturn)
634 for (MachineRegisterInfo::liveout_iterator
635 I = MF->getRegInfo().liveout_begin(),
636 E = MF->getRegInfo().liveout_end(); I != E; ++I)
637 if (!Ret->readsRegister(*I)) {
638 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
639 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
640 }
641
642 // Finally, loop over the final use/def of each reg
643 // in the block and determine if it is dead.
644 for (DenseMap >::iterator
645 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
646 MachineInstr *MI = I->second.first;
647 unsigned idx = I->second.second;
648 MachineOperand &MO = MI->getOperand(idx);
649
650 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
651
652 // A crude approximation of "live-out" calculation
653 bool usedOutsideBlock = isPhysReg ? false :
654 UsedInMultipleBlocks.test(MO.getReg() -
655 TargetRegisterInfo::FirstVirtualRegister);
656
657 // If the machine BB ends in a return instruction, then the value isn't used
658 // outside of the BB.
659 if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) {
660 // DBG_VALUE complicates this: if the only refs of a register outside
661 // this block are DBG_VALUE, we can't keep the reg live just for that,
662 // as it will cause the reg to be spilled at the end of this block when
663 // it wouldn't have been otherwise. Nullify the DBG_VALUEs when that
664 // happens.
665 bool UsedByDebugValueOnly = false;
666 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
667 UE = MRI.reg_end(); UI != UE; ++UI) {
668 // Two cases:
669 // - used in another block
670 // - used in the same block before it is defined (loop)
671 if (UI->getParent() == &MBB &&
672 !(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI)))
673 continue;
674
675 if (UI->isDebugValue()) {
676 UsedByDebugValueOnly = true;
677 continue;
678 }
679
680 // A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
681 UsedInMultipleBlocks.set(MO.getReg() -
682 TargetRegisterInfo::FirstVirtualRegister);
683 usedOutsideBlock = true;
684 UsedByDebugValueOnly = false;
685 break;
686 }
687
688 if (UsedByDebugValueOnly)
689 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
690 UE = MRI.reg_end(); UI != UE; ++UI)
691 if (UI->isDebugValue() &&
692 (UI->getParent() != &MBB ||
693 (MO.isDef() && precedes(&*UI, MI))))
694 UI.getOperand().setReg(0U);
695 }
696
697 // Physical registers and those that are not live-out of the block are
698 // killed/dead at their last use/def within this block.
699 if (isPhysReg || !usedOutsideBlock || BBEndsInReturn) {
700 if (MO.isUse()) {
701 // Don't mark uses that are tied to defs as kills.
702 if (!MI->isRegTiedToDefOperand(idx))
703 MO.setIsKill(true);
704 } else {
705 MO.setIsDead(true);
706 }
707 }
708 }
709 }
710
711 void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
712 // loop over each instruction
713 MachineBasicBlock::iterator MII = MBB.begin();
714
715 DEBUG({
716 const BasicBlock *LBB = MBB.getBasicBlock();
717 if (LBB)
718 dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
719 });
720
721 // Add live-in registers as active.
722 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
723 E = MBB.livein_end(); I != E; ++I) {
724 unsigned Reg = *I;
725 MF->getRegInfo().setPhysRegUsed(Reg);
726 PhysRegsUsed[Reg] = 0; // It is free and reserved now
727 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
728 *SubRegs; ++SubRegs) {
729 if (PhysRegsUsed[*SubRegs] == -2) continue;
730 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
731 MF->getRegInfo().setPhysRegUsed(*SubRegs);
732 }
733 }
734
735 ComputeLocalLiveness(MBB);
736
737 // Otherwise, sequentially allocate each instruction in the MBB.
738 while (MII != MBB.end()) {
739 MachineInstr *MI = MII++;
740 const TargetInstrDesc &TID = MI->getDesc();
741 DEBUG({
742 dbgs() << "\nStarting RegAlloc of: " << *MI;
743 dbgs() << " Regs have values: ";
744 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
745 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
746 dbgs() << "[" << TRI->getName(i)
747 << ",%reg" << PhysRegsUsed[i] << "] ";
748 dbgs() << '\n';
749 });
750
751 // Track registers used by instruction.
752 UsedInInstr.reset();
753
754 // Determine whether this is a copy instruction. The cases where the
755 // source or destination are phys regs are handled specially.
756 unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
757 unsigned SrcCopyPhysReg = 0U;
758 bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
759 SrcCopySubReg, DstCopySubReg);
760 if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
761 SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
762
763 // Loop over the implicit uses, making sure they don't get reallocated.
764 if (TID.ImplicitUses) {
765 for (const unsigned *ImplicitUses = TID.ImplicitUses;
766 *ImplicitUses; ++ImplicitUses)
767 UsedInInstr.set(*ImplicitUses);
768 }
769
770 SmallVector Kills;
771 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
772 MachineOperand &MO = MI->getOperand(i);
773 if (!MO.isReg() || !MO.isKill()) continue;
774
775 if (!MO.isImplicit())
776 Kills.push_back(MO.getReg());
777 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
778 // These are extra physical register kills when a sub-register
779 // is defined (def of a sub-register is a read/mod/write of the
780 // larger registers). Ignore.
781 Kills.push_back(MO.getReg());
782 }
783
784 // If any physical regs are earlyclobber, spill any value they might
785 // have in them, then mark them unallocatable.
786 // If any virtual regs are earlyclobber, allocate them now (before
787 // freeing inputs that are killed).
788 if (MI->isInlineAsm()) {
789 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
790 MachineOperand &MO = MI->getOperand(i);
791 if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() ||
792 !MO.getReg())
793 continue;
794
795 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
796 unsigned DestVirtReg = MO.getReg();
797 unsigned DestPhysReg;
798
799 // If DestVirtReg already has a value, use it.
800 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
801 DestPhysReg = getReg(MBB, MI, DestVirtReg);
802 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
803 markVirtRegModified(DestVirtReg);
804 getVirtRegLastUse(DestVirtReg) =
805 std::make_pair((MachineInstr*)0, 0);
806 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
807 << " to %reg" << DestVirtReg << "\n");
808 MO.setReg(DestPhysReg); // Assign the earlyclobber register
809 } else {
810 unsigned Reg = MO.getReg();
811 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
812 // These are extra physical register defs when a sub-register
813 // is defined (def of a sub-register is a read/mod/write of the
814 // larger registers). Ignore.
815 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
816
817 MF->getRegInfo().setPhysRegUsed(Reg);
818 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
819 PhysRegsUsed[Reg] = 0; // It is free and reserved now
820
821 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
822 *SubRegs; ++SubRegs) {
823 if (PhysRegsUsed[*SubRegs] == -2) continue;
824 MF->getRegInfo().setPhysRegUsed(*SubRegs);
825 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
826 }
827 }
828 }
829 }
830
831 // If a DBG_VALUE says something is located in a spilled register,
832 // change the DBG_VALUE to be undef, which prevents the register
833 // from being reloaded here. Doing that would change the generated
834 // code, unless another use immediately follows this instruction.
835 if (MI->isDebugValue() &&
836 MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
837 unsigned VirtReg = MI->getOperand(0).getReg();
838 if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
839 !getVirt2PhysRegMapSlot(VirtReg))
840 MI->getOperand(0).setReg(0U);
841 }
842
843 // Get the used operands into registers. This has the potential to spill
844 // incoming values if we are out of registers. Note that we completely
845 // ignore physical register uses here. We assume that if an explicit
846 // physical register is referenced by the instruction, that it is guaranteed
847 // to be live-in, or the input is badly hosed.
848 //
849 SmallSet ReloadedRegs;
850 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
851 MachineOperand &MO = MI->getOperand(i);
852 // here we are looking for only used operands (never def&use)
853 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
854 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
855 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
856 isCopy ? DstCopyReg : 0);
857 }
858
859 // If this instruction is the last user of this register, kill the
860 // value, freeing the register being used, so it doesn't need to be
861 // spilled to memory.
862 //
863 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
864 unsigned VirtReg = Kills[i];
865 unsigned PhysReg = VirtReg;
866 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
867 // If the virtual register was never materialized into a register, it
868 // might not be in the map, but it won't hurt to zero it out anyway.
869 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
870 PhysReg = PhysRegSlot;
871 PhysRegSlot = 0;
872 } else if (PhysRegsUsed[PhysReg] == -2) {
873 // Unallocatable register dead, ignore.
874 continue;
875 } else {
876 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
877 "Silently clearing a virtual register?");
878 }
879
880 if (!PhysReg) continue;
881
882 DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
883 << "[%reg" << VirtReg <<"], removing it from live set\n");
884 removePhysReg(PhysReg);
885 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
886 *SubRegs; ++SubRegs) {
887 if (PhysRegsUsed[*SubRegs] != -2) {
888 DEBUG(dbgs() << " Last use of "
889 << TRI->getName(*SubRegs) << "[%reg" << VirtReg
890 <<"], removing it from live set\n");
891 removePhysReg(*SubRegs);
892 }
893 }
894 }
895
896 // Track registers defined by instruction.
897 UsedInInstr.reset();
898
899 // Loop over all of the operands of the instruction, spilling registers that
900 // are defined, and marking explicit destinations in the PhysRegsUsed map.
901 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
902 MachineOperand &MO = MI->getOperand(i);
903 if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() ||
904 MO.isEarlyClobber() ||
905 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
906 continue;
907
908 unsigned Reg = MO.getReg();
909 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
910 // These are extra physical register defs when a sub-register
911 // is defined (def of a sub-register is a read/mod/write of the
912 // larger registers). Ignore.
913 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
914
915 MF->getRegInfo().setPhysRegUsed(Reg);
916 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
917 PhysRegsUsed[Reg] = 0; // It is free and reserved now
918
919 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
920 *SubRegs; ++SubRegs) {
921 if (PhysRegsUsed[*SubRegs] == -2) continue;
922
923 MF->getRegInfo().setPhysRegUsed(*SubRegs);
924 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
925 }
926 }
927
928 // Loop over the implicit defs, spilling them as well.
929 if (TID.ImplicitDefs) {
930 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
931 *ImplicitDefs; ++ImplicitDefs) {
932 unsigned Reg = *ImplicitDefs;
933 if (PhysRegsUsed[Reg] != -2) {
934 spillPhysReg(MBB, MI, Reg, true);
935 PhysRegsUsed[Reg] = 0; // It is free and reserved now
936 }
937 MF->getRegInfo().setPhysRegUsed(Reg);
938 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
939 *SubRegs; ++SubRegs) {
940 if (PhysRegsUsed[*SubRegs] == -2) continue;
941
942 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
943 MF->getRegInfo().setPhysRegUsed(*SubRegs);
944 }
945 }
946 }
947
948 SmallVector DeadDefs;
949 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
950 MachineOperand &MO = MI->getOperand(i);
951 if (MO.isReg() && MO.isDead())
952 DeadDefs.push_back(MO.getReg());
953 }
954
955 // Okay, we have allocated all of the source operands and spilled any values
956 // that would be destroyed by defs of this instruction. Loop over the
957 // explicit defs and assign them to a register, spilling incoming values if
958 // we need to scavenge a register.
959 //
960 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
961 MachineOperand &MO = MI->getOperand(i);
962 if (!MO.isReg() || !MO.isDef() || !MO.getReg() ||
963 MO.isEarlyClobber() ||
964 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
965 continue;
966
967 unsigned DestVirtReg = MO.getReg();
968 unsigned DestPhysReg;
969
970 // If DestVirtReg already has a value, use it.
971 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
972 // If this is a copy try to reuse the input as the output;
973 // that will make the copy go away.
974 // If this is a copy, the source reg is a phys reg, and
975 // that reg is available, use that phys reg for DestPhysReg.
976 // If this is a copy, the source reg is a virtual reg, and
977 // the phys reg that was assigned to that virtual reg is now
978 // available, use that phys reg for DestPhysReg. (If it's now
979 // available that means this was the last use of the source.)
980 if (isCopy &&
981 TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
982 isPhysRegAvailable(SrcCopyReg)) {
983 DestPhysReg = SrcCopyReg;
984 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
985 } else if (isCopy &&
986 TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
987 SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
988 MF->getRegInfo().getRegClass(DestVirtReg)->
989 contains(SrcCopyPhysReg)) {
990 DestPhysReg = SrcCopyPhysReg;
991 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
992 } else
993 DestPhysReg = getReg(MBB, MI, DestVirtReg);
994 }
995 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
996 markVirtRegModified(DestVirtReg);
997 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
998 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
999 << " to %reg" << DestVirtReg << "\n");
1000 MO.setReg(DestPhysReg); // Assign the output register
1001 UsedInInstr.set(DestPhysReg);
1002 }
1003
1004 // If this instruction defines any registers that are immediately dead,
1005 // kill them now.
1006 //
1007 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
1008 unsigned VirtReg = DeadDefs[i];
1009 unsigned PhysReg = VirtReg;
1010 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1011 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
1012 PhysReg = PhysRegSlot;
1013 assert(PhysReg != 0);
1014 PhysRegSlot = 0;
1015 } else if (PhysRegsUsed[PhysReg] == -2) {
1016 // Unallocatable register dead, ignore.
1017 continue;
1018 } else if (!PhysReg)
1019 continue;
1020
1021 DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
1022 << " [%reg" << VirtReg
1023 << "] is never used, removing it from live set\n");
1024 removePhysReg(PhysReg);
1025 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
1026 *AliasSet; ++AliasSet) {
1027 if (PhysRegsUsed[*AliasSet] != -2) {
1028 DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
1029 << " [%reg" << *AliasSet
1030 << "] is never used, removing it from live set\n");
1031 removePhysReg(*AliasSet);
1032 }
1033 }
1034 }
1035
1036 // Finally, if this is a noop copy instruction, zap it. (Except that if
1037 // the copy is dead, it must be kept to avoid messing up liveness info for
1038 // the register scavenger. See pr4100.)
1039 if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
1040 SrcCopySubReg, DstCopySubReg) &&
1041 SrcCopyReg == DstCopyReg && DeadDefs.empty())
1042 MBB.erase(MI);
1043 }
1044
1045 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1046
1047 // Spill all physical registers holding virtual registers now.
1048 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
1049 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
1050 if (unsigned VirtReg = PhysRegsUsed[i])
1051 spillVirtReg(MBB, MI, VirtReg, i);
1052 else
1053 removePhysReg(i);
1054 }
1055 }
1056
1057 /// runOnMachineFunction - Register allocate the whole function
1058 ///
1059 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1060 DEBUG(dbgs() << "Machine Function\n");
1061 MF = &Fn;
1062 TM = &Fn.getTarget();
1063 TRI = TM->getRegisterInfo();
1064 TII = TM->getInstrInfo();
1065
1066 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1067 UsedInInstr.resize(TRI->getNumRegs());
1068
1069 // At various places we want to efficiently check to see whether a register
1070 // is allocatable. To handle this, we mark all unallocatable registers as
1071 // being pinned down, permanently.
1072 {
1073 BitVector Allocable = TRI->getAllocatableSet(Fn);
1074 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1075 if (!Allocable[i])
1076 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1077 }
1078
1079 // initialize the virtual->physical register map to have a 'null'
1080 // mapping for all virtual registers
1081 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1082 StackSlotForVirtReg.grow(LastVirtReg);
1083 Virt2PhysRegMap.grow(LastVirtReg);
1084 Virt2LastUseMap.grow(LastVirtReg);
1085 VirtRegModified.resize(LastVirtReg+1 -
1086 TargetRegisterInfo::FirstVirtualRegister);
1087 UsedInMultipleBlocks.resize(LastVirtReg+1 -
1088 TargetRegisterInfo::FirstVirtualRegister);
1089
1090 // Loop over all of the basic blocks, eliminating virtual register references
1091 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1092 MBB != MBBe; ++MBB)
1093 AllocateBasicBlock(*MBB);
1094
1095 StackSlotForVirtReg.clear();
1096 PhysRegsUsed.clear();
1097 VirtRegModified.clear();
1098 UsedInMultipleBlocks.clear();
1099 Virt2PhysRegMap.clear();
1100 Virt2LastUseMap.clear();
1101 return true;
1102 }
1103
1104 FunctionPass *llvm::createFastRegisterAllocator() {
1105 return new RAFast();
1106 }