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[AVR] Redefine the 'LSL' instruction as an alias of 'ADD' The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341278 91177308-0d34-0410-b5e6-96231b3b80d8 Dylan McKay 2 years ago
6 changed file(s) with 23 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
12501250 bool DstIsDead = MI.getOperand(0).isDead();
12511251 bool DstIsKill = MI.getOperand(1).isKill();
12521252 bool ImpIsDead = MI.getOperand(2).isDead();
1253 OpLo = AVR::LSLRd;
1253 OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
12541254 OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
12551255 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
12561256
12571257 // Low part
12581258 buildMI(MBB, MBBI, OpLo)
12591259 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1260 .addReg(DstLoReg)
12601261 .addReg(DstLoReg, getKillRegState(DstIsKill));
12611262
12621263 auto MIBHI = buildMI(MBB, MBBI, OpHi)
13871388 .addReg(SrcReg, getKillRegState(SrcIsKill));
13881389 }
13891390
1390 buildMI(MBB, MBBI, AVR::LSLRd)
1391 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
13911392 .addReg(DstHiReg, RegState::Define)
1393 .addReg(DstHiReg)
13921394 .addReg(DstHiReg, RegState::Kill);
13931395
13941396 auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
14401440 default:
14411441 llvm_unreachable("Invalid shift opcode!");
14421442 case AVR::Lsl8:
1443 Opc = AVR::LSLRd;
1443 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
14441444 RC = &AVR::GPR8RegClass;
1445 HasRepeatedOperand = true;
14451446 break;
14461447 case AVR::Lsl16:
14471448 Opc = AVR::LSLWRd;
16311631 let Constraints = "$src = $rd",
16321632 Defs = [SREG] in
16331633 {
1634 def LSLRd : FRdRr<0b0000,
1635 0b11,
1636 (outs GPR8:$rd),
1637 (ins GPR8:$src),
1638 "lsl\t$rd",
1639 [(set i8:$rd, (AVRlsl i8:$src)), (implicit SREG)]>;
1634 // 8-bit LSL is an alias of ADD Rd, Rd
16401635
16411636 def LSLWRd : Pseudo<(outs DREGS:$rd),
16421637 (ins DREGS:$src),
17531748 // -------------
17541749 // Clears all bits in a register.
17551750 def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>;
1751
1752 // LSL Rd
1753 // Alias for ADD Rd, Rd
1754 // --------------
1755 // Logical shift left one bit.
1756 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>;
17561757
17571758 def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>;
17581759
20972098 // Lowering of 'tst' node to 'TST' instruction.
20982099 // TST is an alias of AND Rd, Rd.
20992100 def : Pat<(AVRtst i8:$rd),
2100 (ANDRdRr $rd, $rd)>;
2101
2101 (ANDRdRr GPR8:$rd, GPR8:$rd)>;
2102
2103 // Lowering of 'lsl' node to 'LSL' instruction.
2104 // LSL is an alias of 'ADD Rd, Rd'
2105 def : Pat<(AVRlsl i8:$rd),
2106 (ADDRdRr GPR8:$rd, GPR8:$rd)>;
2107
1414
1515 ; CHECK-LABEL: test
1616
17 ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg
17 ; CHECK: $r14 = ADDRdRr $r14, $r14, implicit-def $sreg
1818 ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
1919
2020 $r15r14 = LSLWRd $r15r14, implicit-def $sreg
1616
1717 ; CHECK: $r14 = MOVRdRr $r31
1818 ; CHECK-NEXT: $r15 = MOVRdRr $r31
19 ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
19 ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
2020 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
2121
2222 $r15r14 = SEXT $r31, implicit-def $sreg
1616
1717 ; CHECK: $r14 = MOVRdRr $r31
1818 ; CHECK-NEXT: $r15 = MOVRdRr $r31
19 ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
19 ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
2020 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
2121
2222 $r15r14 = SEXT $r31, implicit-def $sreg