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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s

# GCN-LABEL: name: hazard_smem_war
# GCN:      S_LOAD_DWORD_IMM
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_no_hazard
# GCN:      S_LOAD_DWORD_IMM
# GCN-NEXT: S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_no_hazard
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr3 = S_ADD_U32 $sgpr4, $sgpr5, implicit-def $scc
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_related_clause
# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_WAITCNT
# GCN:      S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_related_clause
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    S_WAITCNT 0
    $sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_branch
# GCN:      S_LOAD_DWORD_IMM
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_branch
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
    successors: %bb.1
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    S_BRANCH %bb.1

  bb.1:
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_cbranch
# GCN:      S_AND_B64
# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_CBRANCH_VCCZ
# GCN-NOT:  $sgpr_null = S_MOV_B32 0
# GCN:      V_CMP_EQ_F32
# GCN:      S_ENDPGM 0
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_cbranch
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    successors: %bb.1, %bb.2
    $vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc

  bb.1:
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0

  bb.2:
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_cbranch_carry
# GCN:      S_AND_B64
# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_CBRANCH_VCCZ
# GCN-NOT:  $sgpr_null = S_MOV_B32 0
# GCN:      V_CMP_EQ_F32
# GCN-NEXT: S_ENDPGM 0
# GCN-NOT:  $sgpr_null = S_MOV_B32 0
# GCN:      V_CMP_EQ_F32
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_cbranch_carry
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    successors: %bb.1, %bb.2
    $vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc

  bb.1:
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0

  bb.2:
    successors: %bb.3
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec

  bb.3:
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_backedge
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
# GCN:      S_LOAD_DWORD_IMM
---
name: hazard_smem_war_backedge
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
    successors: %bb.1
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec

  bb.1:
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    S_BRANCH %bb.0
...

# GCN-LABEL: name: hazard_smem_war_impdef
# GCN:      S_LOAD_DWORD_IMM
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_impdef
body: |
  bb.0:
    liveins: $vcc, $vgpr0
    $sgpr0 = S_LOAD_DWORD_IMM $vcc, 0, 0, 0
    V_CMP_EQ_F32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $exec
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_readlane
# GCN:      S_LOAD_DWORD_IMM
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_READLANE_B32
---
name: hazard_smem_war_readlane
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr0 = V_READLANE_B32 $vgpr0, $sgpr3
    S_ENDPGM 0
...

# GCN-LABEL: name: hazard_smem_war_readfirstlane
# GCN:      S_LOAD_DWORD_IMM
# GCN:      $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_READFIRSTLANE_B32
---
name: hazard_smem_war_readfirstlane
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $vgpr0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
    S_ENDPGM 0
...