llvm.org GIT mirror llvm / release_90 test / CodeGen / AArch64 / aarch64-interleaved-ld-combine.ll
release_90

Tree @release_90 (Download .tar.gz)

aarch64-interleaved-ld-combine.ll @release_90raw · history · blame

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
; RUN: llc < %s | FileCheck --check-prefix AS %s
; RUN: opt -S -interleaved-load-combine < %s | FileCheck %s

; ModuleID = 'aarch64_interleaved-ld-combine.bc'
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "arm64--linux-gnu"

; This should be lowered into LD4
define void @aarch64_ilc_const(<4 x float>* %ptr) {
entry:

;;; Check LLVM transformation
; CHECK-LABEL: @aarch64_ilc_const(
; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 2
; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <16 x float>*
; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, <16 x float>* [[CAST]], align 16
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
; CHECK: ret void

;;; Check if it gets lowerd
; AS-LABEL: aarch64_ilc_const
; AS: ld4
; AS: ret

  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  2
  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  3
  %gep3 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  4
  %gep4 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  5
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %ld3 = load <4 x float>, <4 x float>* %gep3, align 16
  %ld4 = load <4 x float>, <4 x float>* %gep4, align 16
  %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
  %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
  %m0_3   = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7   = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %m8_11  = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m12_15 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  store <4 x float> %m8_11, <4 x float>* %gep3, align 16
  store <4 x float> %m12_15, <4 x float>* %gep4, align 16
  ret void
}

; This should be lowered into LD4
define void @aarch64_ilc_idx(<4 x float>* %ptr, i64 %idx) {
entry:

;;; Check LLVM transformation
; CHECK-LABEL: @aarch64_ilc_idx(
; CHECK-DAG: [[ADD:%.+]] = add i64 %idx, 16
; CHECK-DAG: [[LSHR:%.+]] = lshr i64 [[ADD]], 2
; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 [[LSHR]]
; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <16 x float>*
; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, <16 x float>* [[CAST]], align 16
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
; CHECK: ret void

; AS-LABEL: aarch64_ilc_idx
; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2
; AS-DAG: add [[ADD:x[0-9]+]], [[LSL]], #64
; AS-DAG: and [[AND:x[0-9]+]], [[ADD]], #0xfffffffffffffff0
; AS-DAG: add [[ADR:x[0-9]+]], x0, [[AND]]
; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, {{\[}}[[ADR]]{{\]}}
; AS-DAG: str q[[V0]]
; AS-DAG: str q[[V1]]
; AS-DAG: str q[[V2]]
; AS-DAG: str q[[V3]]
; AS: ret

  %a2 = add i64 %idx, 20
  %idx2 = lshr i64 %a2, 2
  %a3 = add i64 %idx, 24
  %a1 = add i64 %idx, 16
  %idx1 = lshr i64 %a1, 2
  %idx3 = lshr i64 %a3, 2
  %a4 = add i64 %idx, 28
  %idx4 = lshr i64 %a4, 2

  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx2
  %gep4 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx4
  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx1
  %gep3 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx3
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %ld3 = load <4 x float>, <4 x float>* %gep3, align 16
  %ld4 = load <4 x float>, <4 x float>* %gep4, align 16
  %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
  %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
  %m0_3   = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7   = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %m8_11  = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m12_15 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  store <4 x float> %m8_11, <4 x float>* %gep3, align 16
  store <4 x float> %m12_15, <4 x float>* %gep4, align 16
  ret void
}

; This should be lowered into LD4, a offset of has to be taken into account
%struct.ilc = type <{ float, [0 x <4 x float>] }>
define void @aarch64_ilc_struct(%struct.ilc* %ptr, i64 %idx) {
entry:

;;; Check LLVM transformation
; CHECK-LABEL: @aarch64_ilc_struct(
; CHECK-DAG: [[LSHR:%.+]] = lshr i64 %idx, 2
; CHECK-DAG: [[GEP:%.+]] = getelementptr %struct.ilc, %struct.ilc* %ptr, i32 0, i32 1, i64 [[LSHR]]
; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <16 x float>*
; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, <16 x float>* [[CAST]], align 4
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
; CHECK: ret void

; AS-LABEL: aarch64_ilc_struct
; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2
; AS-DAG: add [[ADD:x[0-9]+]], x0, #4
; AS-DAG: and [[AND:x[0-9]+]], [[LSL]], #0xfffffffffffffff0
; AS-DAG: add [[ADR:x[0-9]+]], [[ADD]], [[AND]]
; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, {{\[}}[[ADR]]{{\]}}
; AS-DAG: str q[[V0]]
; AS-DAG: str q[[V1]]
; AS-DAG: str q[[V2]]
; AS-DAG: str q[[V3]]
; AS: ret

  %a1 = add i64 %idx, 4
  %idx2 = lshr i64 %a1, 2
  %a2 = add i64 %idx, 8
  %idx3 = lshr i64 %a2, 2
  %a3 = add i64 %idx, 12
  %idx4 = lshr i64 %a3, 2

  %gep2 = getelementptr %struct.ilc, %struct.ilc* %ptr, i32 0, i32 1, i64 %idx2
  %gep3 = getelementptr %struct.ilc, %struct.ilc* %ptr, i32 0, i32 1, i64 %idx3
  %gep4 = getelementptr %struct.ilc, %struct.ilc* %ptr, i32 0, i32 1, i64 %idx4
  %idx1 = lshr i64 %idx, 2
  %gep1 = getelementptr %struct.ilc, %struct.ilc* %ptr, i32 0, i32 1, i64 %idx1
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 4
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 4
  %ld3 = load <4 x float>, <4 x float>* %gep3, align 4
  %ld4 = load <4 x float>, <4 x float>* %gep4, align 4
  %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
  %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
  %m0_3   = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7   = shufflevector <4 x float> %sv1, <4 x float> %sv3, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %m8_11  = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m12_15 = shufflevector <4 x float> %sv2, <4 x float> %sv4, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  store <4 x float> %m8_11, <4 x float>* %gep3, align 16
  store <4 x float> %m12_15, <4 x float>* %gep4, align 16
  ret void
}

; This should be lowered into LD2
define void @aarch64_ilc_idx_ld2(<4 x float>* %ptr, i64 %idx) {
entry:
; CHECK-LABEL: @aarch64_ilc_idx_ld2(
; CHECK-DAG: [[LSHR:%.+]] = lshr i64 %idx, 2
; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 [[LSHR]]
; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <8 x float>*
; CHECK-DAG: [[LOAD:%.+]] = load <8 x float>, <8 x float>* [[CAST]], align 16
; CHECK: %{{.* }}= shufflevector <8 x float> [[LOAD]], <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK: %{{.* }}= shufflevector <8 x float> [[LOAD]], <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
; CHECK-DAG: ret void

; AS-LABEL: aarch64_ilc_idx_ld2
; AS: ld2
; AS: ret

  %idx1 = lshr i64 %idx, 2
  %a1 = add i64 %idx, 4
  %idx2 = lshr i64 %a1, 2

  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx1
  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx2
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1
  store <4 x float> %m4_7, <4 x float>* %gep2
  ret void
}

; This should be lowered into LD3
define void @aarch64_ilc_idx_ld3(<4 x float>* %ptr, i64 %idx) {
entry:
; CHECK-LABEL: @aarch64_ilc_idx_ld3(
; CHECK-DAG: [[LSHR:%.+]] = lshr i64 %idx, 2
; CHECK-DAG: [[GEP:%.+]] = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 [[LSHR]]
; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <12 x float>*
; CHECK-DAG: [[LOAD:%.+]] = load <12 x float>, <12 x float>* [[CAST]], align 16
; CHECK: %{{.* }}= shufflevector <12 x float> [[LOAD]], <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
; CHECK: %{{.* }}= shufflevector <12 x float> [[LOAD]], <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
; CHECK: %{{.* }}= shufflevector <12 x float> [[LOAD]], <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
; CHECK-DAG: ret void

; AS-LABEL: aarch64_ilc_idx_ld3
; AS: ld3
; AS: ret

  %idx1 = lshr i64 %idx, 2
  %a1 = add i64 %idx, 4
  %idx2 = lshr i64 %a1, 2
  %a2 = add i64 %idx, 8
  %idx3 = lshr i64 %a2, 2

  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx1
  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx2
  %gep3 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64  %idx3
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %ld3 = load <4 x float>, <4 x float>* %gep3, align 16

  %sv1 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 3, i32 6, i32 undef>
  %sv2 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 4, i32 7, i32 undef>
  %sv3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
  %m0_3 = shufflevector <4 x float> %sv1, <4 x float> %ld3, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  %m4_7 = shufflevector <4 x float> %sv2, <4 x float> %ld3, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
  %m8_11 = shufflevector <4 x float> %sv3, <4 x float> %ld3, <4 x i32> <i32 0, i32 1, i32 4, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  store <4 x float> %m8_11, <4 x float>* %gep3, align 16
  ret void
}
;  %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 undef, i32 4, i32 undef>

; This must not be lowered
define void @aarch64_ilc_i32_idx(<4 x float>* %ptr, i32 %idx) {
; CHECK-LABEL: @aarch64_ilc_i32_idx(
; CHECK: %idx1 = lshr i32 %idx, 2
; CHECK-NEXT: %a1 = add i32 %idx, 4
; CHECK-NEXT: %idx2 = lshr i32 %a1, 2
; CHECK-NEXT: %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 %idx1
; CHECK-NEXT: %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 %idx2
; CHECK-NEXT: %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
; CHECK-NEXT: %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
; CHECK-NEXT: %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
; CHECK-NEXT: store <4 x float> %m0_3, <4 x float>* %gep1, align 16
; CHECK-NEXT: store <4 x float> %m4_7, <4 x float>* %gep2, align 16
; CHECK-NEXT: ret void

; AS-LABEL: aarch64_ilc_i32_idx
; AS-DAG: @function
; AS-NOT: ld2
; AS-NOT: ld3
; AS-NOT: ld4
; AS-DAG: ret

entry:
  %idx1 = lshr i32 %idx, 2
  %a1 = add i32 %idx, 4
  %idx2 = lshr i32 %a1, 2

  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 %idx1
  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 %idx2
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  ret void
}

; Volatile loads must not be lowered
define void @aarch64_ilc_volatile(<4 x float>* %ptr) {
; CHECK-LABEL: @aarch64_ilc_volatile(
; CHECK: %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 0
; CHECK-NEXT: %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 1
; CHECK-NEXT: %ld1 = load volatile <4 x float>, <4 x float>* %gep1, align 16
; CHECK-NEXT: %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
; CHECK-NEXT: %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
; CHECK-NEXT: store <4 x float> %m0_3, <4 x float>* %gep1, align 16
; CHECK-NEXT: store <4 x float> %m4_7, <4 x float>* %gep2, align 16
; CHECK-NEXT: ret void

; AS-LABEL: aarch64_ilc_volatile
; AS-DAG: @function
; AS-NOT: ld2
; AS-NOT: ld3
; AS-NOT: ld4
; AS-DAG: ret

entry:
  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 0
  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 1
  %ld1 = load volatile <4 x float>, <4 x float>* %gep1, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  ret void
}

; This must not be lowered
define void @aarch64_ilc_depmem(<4 x float>* %ptr, i32 %idx) {
entry:
; CHECK-LABEL: @aarch64_ilc_depmem(
; CHECK: %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 0
; CHECK-NEXT: %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 1
; CHECK-NEXT: %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
; CHECK-NEXT: store <4 x float> %ld1, <4 x float>* %gep2, align 16
; CHECK-NEXT: %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
; CHECK-NEXT: %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
; CHECK-NEXT: store <4 x float> %m0_3, <4 x float>* %gep1, align 16
; CHECK-NEXT: store <4 x float> %m4_7, <4 x float>* %gep2, align 16
; CHECK-NEXT: ret void

; AS-LABEL: aarch64_ilc_depmem
; AS-DAG: @function
; AS-NOT: ld2
; AS-NOT: ld3
; AS-NOT: ld4
; AS-DAG: ret

  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 0
  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i32 1
  %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
  store <4 x float> %ld1, <4 x float>* %gep2, align 16
  %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
  %m0_3 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %m4_7 = shufflevector <4 x float> %ld1, <4 x float> %ld2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>

  store <4 x float> %m0_3, <4 x float>* %gep1, align 16
  store <4 x float> %m4_7, <4 x float>* %gep2, align 16
  ret void
}

; This cannot be converted - insertion position cannot be determined
define void @aarch64_no_insertion_pos(float* %ptr) {
entry:
; CHECK-LABEL: @aarch64_no_insertion_pos(
; CHECK: %p0 = getelementptr inbounds float, float* %ptr, i32 0
; CHECK-NEXT: %p1 = getelementptr inbounds float, float* %ptr, i32 4
; CHECK-NEXT: %b0 = bitcast float* %p0 to <5 x float>*
; CHECK-NEXT: %b1 = bitcast float* %p1 to <5 x float>*
; CHECK-NEXT: %l0 = load <5 x float>, <5 x float>* %b0
; CHECK-NEXT: %l1 = load <5 x float>, <5 x float>* %b1
; CHECK-NEXT: %s0 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 1, i32 3, i32 6, i32 8>
; CHECK-NEXT: %s1 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 2, i32 4, i32 7, i32 9>
; CHECK-NEXT: ret void

  %p0 = getelementptr inbounds float, float* %ptr, i32 0
  %p1 = getelementptr inbounds float, float* %ptr, i32 4
  %b0 = bitcast float* %p0 to <5 x float>*
  %b1 = bitcast float* %p1 to <5 x float>*
  %l0 = load <5 x float>, <5 x float>* %b0
  %l1 = load <5 x float>, <5 x float>* %b1
  %s0 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 1, i32 3, i32 6, i32 8>
  %s1 = shufflevector <5 x float> %l0, <5 x float> %l1, <4 x i32> <i32 2, i32 4, i32 7, i32 9>
  ret void
}

; This cannot be converted - the insertion position does not dominate all
; uses
define void @aarch64_insertpos_does_not_dominate(float* %ptr) {
entry:
; CHECK-LABEL: @aarch64_insertpos_does_not_dominate(
; CHECK: %p0 = getelementptr inbounds float, float* %ptr, i32 0
; CHECK-NEXT: %p1 = getelementptr inbounds float, float* %ptr, i32 1
; CHECK-NEXT: %b0 = bitcast float* %p0 to <7 x float>*
; CHECK-NEXT: %b1 = bitcast float* %p1 to <7 x float>*
; CHECK-NEXT: %l1 = load <7 x float>, <7 x float>* %b1
; CHECK-NEXT: %s1 = shufflevector <7 x float> %l1, <7 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: %l0 = load <7 x float>, <7 x float>* %b0
; CHECK-NEXT: %s0 = shufflevector <7 x float> %l0, <7 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: ret void
  %p0 = getelementptr inbounds float, float* %ptr, i32 0
  %p1 = getelementptr inbounds float, float* %ptr, i32 1
  %b0 = bitcast float* %p0 to <7 x float>*
  %b1 = bitcast float* %p1 to <7 x float>*
  %l1 = load <7 x float>, <7 x float>* %b1
  %s1 = shufflevector <7 x float> %l1, <7 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %l0 = load <7 x float>, <7 x float>* %b0
  %s0 = shufflevector <7 x float> %l0, <7 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  ret void
}