Tree @release_60 (Download .tar.gz)
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- AlignedBundling
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- Windows
- 2010-11-30-reloc-movt.s
- 2013-03-18-Br-to-label-named-like-reg.s
- align_arm_2_thumb.s
- align_thumb_2_arm.s
- aligned-blx.s
- arm-aliases.s
- arm-arithmetic-aliases.s
- arm-branch-errors.s
- arm-branches.s
- arm-elf-relocation-diagnostics.s
- arm-elf-relocations.s
- arm-elf-symver.s
- arm-it-block.s
- arm-ldrd.s
- arm-load-store-multiple-deprecated.s
- arm-macho-calls.s
- arm-memory-instructions.s
- arm-qualifier-diagnostics.s
- arm-shift-encoding.s
- arm-thumb-cpus-default.s
- arm-thumb-cpus.s
- arm-thumb-tail-call.ll
- arm-thumb-trustzone.s
- arm-trustzone.s
- arm11-hint-instr.s
- arm_addrmode2.s
- arm_addrmode3.s
- arm_fixups.s
- arm_instructions.s
- armv8.2a-dotprod-a32.s
- armv8.2a-dotprod-error.s
- armv8.2a-dotprod-t32.s
- armv8.3a-js.s
- assembly-default-build-attributes.s
- basic-arm-instructions-v8.1a.s
- basic-arm-instructions-v8.s
- basic-arm-instructions.s
- basic-thumb-instructions.s
- basic-thumb2-instructions-v8.s
- basic-thumb2-instructions.s
- big-endian-arm-fixup.s
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- big-endian-thumb2-fixup.s
- bkpt.s
- bracket-darwin.s
- bracket-exprs.s
- branch-disassemble.s
- cmp-immediate-fixup-error.s
- cmp-immediate-fixup-error2.s
- cmp-immediate-fixup.s
- cmp-immediate-fixup2.s
- coff-debugging-secrel.ll
- coff-file.s
- coff-function-type-info.ll
- coff-relocations.s
- comment.s
- complex-operands.s
- coproc-diag.s
- cps.s
- cpu-test.s
- crc32-thumb.s
- crc32.s
- cxx-global-constructor.ll
- d16.s
- data-in-code.ll
- deprecated-v8.s
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- dfb.s
- diagnostics-noneon.s
- diagnostics.s
- directive-align.s
- directive-arch-armv2.s
- directive-arch-armv2a.s
- directive-arch-armv3.s
- directive-arch-armv3m.s
- directive-arch-armv4.s
- directive-arch-armv4t.s
- directive-arch-armv5.s
- directive-arch-armv5t.s
- directive-arch-armv5te.s
- directive-arch-armv6-m.s
- directive-arch-armv6.s
- directive-arch-armv6k.s
- directive-arch-armv6t2.s
- directive-arch-armv6z.s
- directive-arch-armv7-a.s
- directive-arch-armv7-m.s
- directive-arch-armv7-r.s
- directive-arch-armv7.s
- directive-arch-armv7a.s
- directive-arch-armv7e-m.s
- directive-arch-armv7em.s
- directive-arch-armv7m.s
- directive-arch-armv7r.s
- directive-arch-armv8-a.s
- directive-arch-armv8.2-a.s
- directive-arch-armv8a.s
- directive-arch-iwmmxt.s
- directive-arch-iwmmxt2.s
- directive-arch-mode-switch.s
- directive-arch-semantic-action.s
- directive-arch_extension-crc.s
- directive-arch_extension-crypto.s
- directive-arch_extension-fp.s
- directive-arch_extension-idiv.s
- directive-arch_extension-mode-switch.s
- directive-arch_extension-mp.s
- directive-arch_extension-sec.s
- directive-arch_extension-simd.s
- directive-arch_extension-toggle.s
- directive-arch_extension-unsupported.s
- directive-cpu.s
- directive-eabi_attribute-diagnostics.s
- directive-eabi_attribute-overwrite.s
- directive-eabi_attribute.s
- directive-even.s
- directive-fpu-diagnostics.s
- directive-fpu-instrs.s
- directive-fpu-multiple.s
- directive-fpu-softvfp.s
- directive-fpu.s
- directive-literals.s
- directive-object_arch-2.s
- directive-object_arch-3.s
- directive-object_arch-diagnostics.s
- directive-object_arch.s
- directive-thumb_func.s
- directive-tlsdescseq-diagnostics.s
- directive-tlsdescseq.s
- directive-type-diagnostics.s
- directive-unsupported.s
- directive-word-diagnostics.s
- directive_parsing.s
- dot-req-case-insensitive.s
- dot-req.s
- dwarf-asm-multiple-sections-dwarf-2.s
- dwarf-asm-multiple-sections.s
- dwarf-asm-no-code.s
- dwarf-asm-nonstandard-section.s
- dwarf-asm-single-section.s
- dwarf-cfi-initial-state.s
- eh-compact-pr0.s
- eh-compact-pr1.s
- eh-directive-cantunwind-diagnostics.s
- eh-directive-cantunwind.s
- eh-directive-fnend-diagnostics.s
- eh-directive-fnstart-diagnostics.s
- eh-directive-handlerdata.s
- eh-directive-integrated-test.s
- eh-directive-movsp-diagnostics.s
- eh-directive-movsp.s
- eh-directive-multiple-offsets.s
- eh-directive-pad-diagnostics.s
- eh-directive-pad.s
- eh-directive-personality-diagnostics.s
- eh-directive-personality.s
- eh-directive-personalityindex-diagnostics.s
- eh-directive-personalityindex.s
- eh-directive-save-diagnostics.s
- eh-directive-save.s
- eh-directive-section-comdat.s
- eh-directive-section-multiple-func.s
- eh-directive-section.s
- eh-directive-setfp-diagnostics.s
- eh-directive-setfp.s
- eh-directive-text-section-multiple-func.s
- eh-directive-text-section.s
- eh-directive-unwind_raw-diagnostics.s
- eh-directive-unwind_raw.s
- eh-directive-vsave-diagnostics.s
- eh-directive-vsave.s
- eh-link.s
- ehabi-personality-abs.s
- elf-eflags-eabi.s
- elf-jump24-fixup.s
- elf-movt.s
- elf-reloc-01.s
- elf-reloc-02.s
- elf-reloc-03.s
- elf-reloc-condcall.s
- elf-thumbfunc-reloc.s
- elf-thumbfunc-reloc2.s
- elf-thumbfunc.s
- error-location-ldr-pseudo.s
- error-location-post-layout.s
- error-location.s
- fconst.s
- fixup-cpu-mode.s
- fp-armv8.s
- fp-const-errors.s
- full_line_comment.s
- fullfp16-neg.s
- fullfp16-neon-neg.s
- fullfp16-neon.s
- fullfp16.s
- gas-compl-copr-reg.s
- hilo-16bit-relocations.s
- idiv.s
- implicit-it-generation.s
- implicit-it.s
- inline-asm-diags.ll
- inline-asm-srcloc.ll
- inline-comments-arm.ll
- inst-arm-suffixes.s
- inst-constant-required.s
- inst-directive-emit.s
- inst-directive.s
- inst-overflow.s
- inst-thumb-overflow-2.s
- inst-thumb-overflow.s
- inst-thumb-suffixes.s
- invalid-barrier.s
- invalid-crc32.s
- invalid-fp-armv8.s
- invalid-hint-arm.s
- invalid-hint-thumb.s
- invalid-idiv.s
- invalid-instructions-spellcheck.s
- invalid-neon-v8.s
- invalid-special-reg.s
- invalid-vector-index.s
- ldr-pseudo-cond-darwin.s
- ldr-pseudo-cond.s
- ldr-pseudo-darwin.s
- ldr-pseudo-obj-errors.s
- ldr-pseudo-parse-errors.s
- ldr-pseudo-unpredictable.s
- ldr-pseudo-wide.s
- ldr-pseudo.s
- ldrd-strd-gnu-arm-bad-imm.s
- ldrd-strd-gnu-arm-bad-regs.s
- ldrd-strd-gnu-arm.s
- ldrd-strd-gnu-bad-inst.s
- ldrd-strd-gnu-sp.s
- ldrd-strd-gnu-thumb-bad-regs.s
- ldrd-strd-gnu-thumb.s
- lit.local.cfg
- load-store-acquire-release-v8-thumb.s
- load-store-acquire-release-v8.s
- lsl-zero-errors.s
- lsl-zero.s
- ltorg-darwin.s
- ltorg-range.s
- ltorg.s
- macho-movwt.s
- macho-relocs-with-addend.s
- macho-word-reloc-thumb.s
- mapping-initial.s
- mapping-within-section.s
- mappingsymbols.s
- misaligned-blx.s
- mixed-arm-thumb-bl-fixup.ll
- mode-switch.s
- modified-immediate-fixup-error.s
- modified-immediate-fixup.s
- move-banked-regs.s
- mul-v4.s
- multi-section-mapping.s
- negative-immediates-fail.s
- negative-immediates-thumb1-fail.s
- negative-immediates-thumb1.s
- negative-immediates.s
- neon-abs-encoding.s
- neon-absdiff-encoding.s
- neon-add-encoding.s
- neon-bitcount-encoding.s
- neon-bitwise-encoding.s
- neon-cmp-encoding.s
- neon-complex.s
- neon-convert-encoding.s
- neon-crypto.s
- neon-dup-encoding.s
- neon-minmax-encoding.s
- neon-mov-encoding.s
- neon-mov-vfp.s
- neon-mul-accum-encoding.s
- neon-mul-encoding.s
- neon-neg-encoding.s
- neon-pairwise-encoding.s
- neon-reciprocal-encoding.s
- neon-reverse-encoding.s
- neon-satshift-encoding.s
- neon-shift-encoding.s
- neon-shiftaccum-encoding.s
- neon-shuffle-encoding.s
- neon-sub-encoding.s
- neon-table-encoding.s
- neon-v8.s
- neon-vcvt-fp16.s
- neon-vld-encoding.s
- neon-vld-vst-align.s
- neon-vst-encoding.s
- neon-vswp.s
- neont2-abs-encoding.s
- neont2-absdiff-encoding.s
- neont2-add-encoding.s
- neont2-bitcount-encoding.s
- neont2-bitwise-encoding.s
- neont2-cmp-encoding.s
- neont2-convert-encoding.s
- neont2-dup-encoding.s
- neont2-minmax-encoding.s
- neont2-mov-encoding.s
- neont2-mul-accum-encoding.s
- neont2-mul-encoding.s
- neont2-neg-encoding.s
- neont2-pairwise-encoding.s
- neont2-reciprocal-encoding.s
- neont2-reverse-encoding.s
- neont2-satshift-encoding.s
- neont2-shift-encoding.s
- neont2-shiftaccum-encoding.s
- neont2-shuffle-encoding.s
- neont2-sub-encoding.s
- neont2-table-encoding.s
- neont2-vld-encoding.s
- neont2-vst-encoding.s
- not-armv4.s
- obsolete-v8.s
- pkhbt-archs.s
- pool.s
- pr11877.s
- pr22395-2.s
- pr22395.s
- preserve-comments-arm.s
- quad-relocation.s
- ras-extension.s
- register-token-source-loc.s
- relocated-mapping.s
- simple-fp-encoding.s
- single-precision-fp.s
- sub-expr-imm.s
- symbol-variants-errors.s
- symbol-variants.s
- t2-modified-immediate-fixup-error1.s
- t2-modified-immediate-fixup-error2.s
- t2-modified-immediate-fixup.s
- target-expressions.s
- thumb-add-sub-width.s
- thumb-branch-errors.s
- thumb-branches.s
- thumb-cb-offsets.s
- thumb-cb-thumbfunc.s
- thumb-diagnostics.s
- thumb-far-jump.s
- thumb-fp-armv8.s
- thumb-hints.s
- thumb-invalid-crypto.txt
- thumb-load-store-multiple.s
- thumb-mov.s
- thumb-movwt-reloc.s
- thumb-neon-crypto.s
- thumb-neon-v8.s
- thumb-not-mclass.s
- thumb-only-conditionals.s
- thumb-shift-encoding.s
- thumb-st_other.s
- thumb-types.s
- thumb.s
- thumb1-branch-reloc.s
- thumb1-relax-8m-baseline.s
- thumb1-relax-adr.s
- thumb1-relax-bcc.s
- thumb1-relax-br.s
- thumb1-relax-ldrlit.s
- thumb1-relax.s
- thumb2-b.w-encodingT4.s
- thumb2-beq-fixup.s
- thumb2-branches.s
- thumb2-bxj-v8.s
- thumb2-bxj.s
- thumb2-cbn-to-next-inst.s
- thumb2-diagnostics.s
- thumb2-dsp-diag.s
- thumb2-exception-return-mclass.s
- thumb2-ldrb-ldrh.s
- thumb2-ldrd.s
- thumb2-ldrexd-strexd.s
- thumb2-mclass.s
- thumb2-narrow-dp.ll
- thumb2-pldw.s
- thumb2-strd.s
- thumb2be-b.w-encoding.s
- thumb2be-beq.w-encoding.s
- thumb2be-movt-encoding.s
- thumb2be-movw-encoding.s
- thumb_rewrites.s
- thumb_set-diagnostics.s
- thumb_set.s
- thumbv7em.s
- thumbv7m.s
- thumbv8m.s
- tls-directives.s
- twice.ll
- udf-arm-diagnostics.s
- udf-arm.s
- udf-thumb-2-diagnostics.s
- udf-thumb-2.s
- udf-thumb-diagnostics.s
- udf-thumb.s
- unpred-control-flow-in-it-block.s
- unwind-stack-diagnostics.s
- v7k-dsp.s
- v8_IT_manual.s
- variant-diagnostics.s
- vfp-aliases-diagnostics.s
- vfp-aliases.s
- vfp4.s
- virtexts-arm.s
- virtexts-thumb.s
- vldm-vstm-diags.s
- vmov-vmvn-byte-replicate.s
- vmov-vmvn-illegal-cases.s
- vmrs_vmsr.s
- vorr-vbic-illegal-cases.s
- vpush-vpop.s
eh-directive-save.s @release_60 — raw · history · blame
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@ RUN: | llvm-readobj -s -sd | FileCheck %s
@ Check the .save directive
@ The .save directive records the GPR registers which are pushed to the
@ stack. There are 4 different unwind opcodes:
@
@ 0xB100: pop r[3:0]
@ 0xA0: pop r[(4+x):4] @ r[4+x]-r[4] must be consecutive.
@ 0xA8: pop r14, r[(4+x):4] @ r[4+x]-r[4] must be consecutive.
@ 0x8000: pop r[15:4]
@
@ If register list specifed by .save directive is possible to be encoded
@ by 0xA0 or 0xA8, then the assembler should prefer them over 0x8000.
.syntax unified
@-------------------------------------------------------------------------------
@ TEST1
@-------------------------------------------------------------------------------
.section .TEST1
.globl func1a
.align 2
.type func1a,%function
.fnstart
func1a:
.save {r0}
push {r0}
pop {r0}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func1b
.align 2
.type func1b,%function
.fnstart
func1b:
.save {r0, r1}
push {r0, r1}
pop {r0, r1}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func1c
.align 2
.type func1c,%function
.fnstart
func1c:
.save {r0, r2}
push {r0, r2}
pop {r0, r2}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func1d
.align 2
.type func1d,%function
.fnstart
func1d:
.save {r1, r2}
push {r1, r2}
pop {r1, r2}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func1e
.align 2
.type func1e,%function
.fnstart
func1e:
.save {r0, r1, r2, r3}
push {r0, r1, r2, r3}
pop {r0, r1, r2, r3}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
@-------------------------------------------------------------------------------
@ The assembler should emit 0xB000 unwind opcode.
@-------------------------------------------------------------------------------
@ CHECK: Section {
@ CHECK: Name: .ARM.extab.TEST1
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 B001B100 00000000 B003B100 |................|
@ CHECK: 0010: 00000000 B005B100 00000000 B006B100 |................|
@ CHECK: 0020: 00000000 B00FB100 |........|
@ CHECK: )
@ CHECK: }
@-------------------------------------------------------------------------------
@ TEST2
@-------------------------------------------------------------------------------
.section .TEST2
.globl func2a
.align 2
.type func2a,%function
.fnstart
func2a:
.save {r4}
push {r4}
pop {r4}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func2b
.align 2
.type func2b,%function
.fnstart
func2b:
.save {r4, r5}
push {r4, r5}
pop {r4, r5}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func2c
.align 2
.type func2c,%function
.fnstart
func2c:
.save {r4, r5, r6, r7, r8, r9, r10, r11}
push {r4, r5, r6, r7, r8, r9, r10, r11}
pop {r4, r5, r6, r7, r8, r9, r10, r11}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
@-------------------------------------------------------------------------------
@ The assembler should emit 0xA0 unwind opcode.
@-------------------------------------------------------------------------------
@ CHECK: Section {
@ CHECK: Name: .ARM.extab.TEST2
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 B0B0A000 00000000 B0B0A100 |................|
@ CHECK: 0010: 00000000 B0B0A700 |........|
@ CHECK: )
@ CHECK: }
@-------------------------------------------------------------------------------
@ TEST3
@-------------------------------------------------------------------------------
.section .TEST3
.globl func3a
.align 2
.type func3a,%function
.fnstart
func3a:
.save {r4, r14}
push {r4, r14}
pop {r4, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func3b
.align 2
.type func3b,%function
.fnstart
func3b:
.save {r4, r5, r14}
push {r4, r5, r14}
pop {r4, r5, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func3c
.align 2
.type func3c,%function
.fnstart
func3c:
.save {r4, r5, r6, r7, r8, r9, r10, r11, r14}
push {r4, r5, r6, r7, r8, r9, r10, r11, r14}
pop {r4, r5, r6, r7, r8, r9, r10, r11, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
@-------------------------------------------------------------------------------
@ The assembler should emit 0xA8 unwind opcode.
@-------------------------------------------------------------------------------
@ CHECK: Section {
@ CHECK: Name: .ARM.extab.TEST3
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 B0B0A800 00000000 B0B0A900 |................|
@ CHECK: 0010: 00000000 B0B0AF00 |........|
@ CHECK: )
@ CHECK: }
@-------------------------------------------------------------------------------
@ TEST4
@-------------------------------------------------------------------------------
.section .TEST4
.globl func4a
.align 2
.type func4a,%function
.fnstart
func4a:
.save {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func4b
.align 2
.type func4b,%function
.fnstart
func4b:
@ Note: r7 is missing intentionally.
.save {r4, r5, r6, r8, r9, r10, r11}
push {r4, r5, r6, r8, r9, r10, r11}
pop {r4, r5, r6, r8, r9, r10, r11}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func4c
.align 2
.type func4c,%function
.fnstart
func4c:
@ Note: r7 is missing intentionally.
.save {r4, r5, r6, r8, r9, r10, r11, r14}
push {r4, r5, r6, r8, r9, r10, r11, r14}
pop {r4, r5, r6, r8, r9, r10, r11, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func4d
.align 2
.type func4d,%function
.fnstart
func4d:
@ Note: The register list is not start with r4.
.save {r5, r6, r7}
push {r5, r6, r7}
pop {r5, r6, r7}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func4e
.align 2
.type func4e,%function
.fnstart
func4e:
@ Note: The register list is not start with r4.
.save {r5, r6, r7, r14}
push {r5, r6, r7, r14}
pop {r5, r6, r7, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
@-------------------------------------------------------------------------------
@ The assembler should emit 0x8000 unwind opcode.
@-------------------------------------------------------------------------------
@ CHECK: Section {
@ CHECK: Name: .ARM.extab.TEST4
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 B0FF8500 00000000 B0F78000 |................|
@ CHECK: 0010: 00000000 B0F78400 00000000 B00E8000 |................|
@ CHECK: 0020: 00000000 B00E8400 |........|
@ CHECK: )
@ CHECK: }
@-------------------------------------------------------------------------------
@ TEST5
@-------------------------------------------------------------------------------
.section .TEST5
.globl func5a
.align 2
.type func5a,%function
.fnstart
func5a:
.save {r0, r1, r2, r3, r4, r5, r6}
push {r0, r1, r2, r3, r4, r5, r6}
pop {r0, r1, r2, r3, r4, r5, r6}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
.globl func5b
.align 2
.type func5b,%function
.fnstart
func5b:
.save {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
bx lr
.personality __gxx_personality_v0
.handlerdata
.fnend
@-------------------------------------------------------------------------------
@ Check the order of unwind opcode to pop registers.
@ 0xB10F "pop {r0-r3}" should be emitted before 0xA2 "pop {r4-r6}".
@ 0xB10F "pop {r0-r3}" should be emitted before 0x85FF "pop {r4-r12, r14}".
@-------------------------------------------------------------------------------
@ CHECK: Section {
@ CHECK: Name: .ARM.extab.TEST5
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 A20FB100 00000000 850FB101 |................|
@ CHECK: 0010: B0B0B0FF |....|
@ CHECK: )
@ CHECK: }
|