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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O3 < %s | FileCheck %s

; Test case derived from bug report 15031.  The code in the post-RA
; scheduler to break critical anti-dependencies was failing to check
; whether an instruction had more than one definition, and ensuring
; that any additional definitions interfered with the choice of a new
; register.  As a result, this test originally caused this to be
; generated:
;
;   lbzu 3, 1(3)
;
; which is illegal, since it requires register 3 to both receive the
; loaded value and receive the updated address.  With the fix to bug
; 15031, a different register is chosen to receive the loaded value.

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

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%"class.llvm::TargetRegisterClass" = type { %"class.llvm::MCRegisterClass"*, i32*, i32*, i16*, %"class.llvm::TargetRegisterClass"**, void (%"class.llvm::ArrayRef"*, %"class.llvm::MachineFunction"*)* }
%"class.llvm::ArrayRef" = type { i16*, i64 }
%"class.llvm::IndexedMap" = type { %"class.std::vector.140", %"struct.std::pair.145", %"struct.llvm::VirtReg2IndexFunctor" }
%"class.std::vector.140" = type { %"struct.std::_Vector_base.141" }
%"struct.std::_Vector_base.141" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass *, llvm::MachineOperand *>, std::allocator<std::pair<const llvm::TargetRegisterClass *, llvm::MachineOperand *> > >::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass *, llvm::MachineOperand *>, std::allocator<std::pair<const llvm::TargetRegisterClass *, llvm::MachineOperand *> > >::_Vector_impl" = type { %"struct.std::pair.145"*, %"struct.std::pair.145"*, %"struct.std::pair.145"* }
%"struct.std::pair.145" = type { %"class.llvm::TargetRegisterClass"*, %"class.llvm::MachineOperand"* }
%"class.llvm::MachineOperand" = type { i8, [3 x i8], %union.anon, %"class.llvm::MachineInstr"*, %union.anon.188 }
%union.anon = type { i32 }
%union.anon.188 = type { %struct.anon }
%struct.anon = type { %"class.llvm::MachineOperand"*, %"class.llvm::MachineOperand"* }
%"struct.llvm::VirtReg2IndexFunctor" = type { i8 }
%"class.llvm::IndexedMap.146" = type { %"class.std::vector.147", %"struct.std::pair.152", %"struct.llvm::VirtReg2IndexFunctor" }
%"class.std::vector.147" = type { %"struct.std::_Vector_base.148" }
%"struct.std::_Vector_base.148" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>, std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>, std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" = type { %"struct.std::pair.152"*, %"struct.std::pair.152"*, %"struct.std::pair.152"* }
%"struct.std::pair.152" = type { i32, i32 }
%"class.llvm::BitVector" = type { i64*, i32, i32 }
%"struct.llvm::MachineFunctionInfo" = type { i32 (...)** }
%"class.llvm::MachineFrameInfo" = type opaque
%"class.llvm::MachineConstantPool" = type { %"class.llvm::DataLayout"*, i32, %"class.std::vector.153", %"class.llvm::DenseSet" }
%"class.llvm::DataLayout" = type opaque
%"class.std::vector.153" = type { %"struct.std::_Vector_base.154" }
%"struct.std::_Vector_base.154" = type { %"struct.std::_Vector_base<llvm::MachineConstantPoolEntry, std::allocator<llvm::MachineConstantPoolEntry> >::_Vector_impl" }
%"struct.std::_Vector_base<llvm::MachineConstantPoolEntry, std::allocator<llvm::MachineConstantPoolEntry> >::_Vector_impl" = type { %"class.llvm::MachineConstantPoolEntry"*, %"class.llvm::MachineConstantPoolEntry"*, %"class.llvm::MachineConstantPoolEntry"* }
%"class.llvm::MachineConstantPoolEntry" = type { %union.anon.158, i32 }
%union.anon.158 = type { %"class.llvm::Constant"* }
%"class.llvm::Constant" = type { %"class.llvm::User" }
%"class.llvm::DenseSet" = type { %"class.llvm::DenseMap.159" }
%"class.llvm::DenseMap.159" = type { %"struct.std::pair.162"*, i32, i32, i32 }
%"struct.std::pair.162" = type { %"class.llvm::MachineConstantPoolValue"*, i8 }
%"class.llvm::MachineConstantPoolValue" = type { i32 (...)**, %"class.llvm::Type"* }
%"class.llvm::MachineJumpTableInfo" = type opaque
%"class.std::vector.163" = type { %"struct.std::_Vector_base.164" }
%"struct.std::_Vector_base.164" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock *, std::allocator<llvm::MachineBasicBlock *> >::_Vector_impl" }
%"struct.std::_Vector_base<llvm::MachineBasicBlock *, std::allocator<llvm::MachineBasicBlock *> >::_Vector_impl" = type { %"class.llvm::MachineBasicBlock"**, %"class.llvm::MachineBasicBlock"**, %"class.llvm::MachineBasicBlock"** }
%"class.llvm::Recycler" = type { %"class.llvm::iplist.168" }
%"class.llvm::iplist.168" = type { %"struct.llvm::ilist_traits.169", %"struct.llvm::RecyclerStruct"* }
%"struct.llvm::ilist_traits.169" = type { %"struct.llvm::RecyclerStruct" }
%"struct.llvm::RecyclerStruct" = type { %"struct.llvm::RecyclerStruct"*, %"struct.llvm::RecyclerStruct"* }
%"class.llvm::ArrayRecycler" = type { %"class.llvm::SmallVector.174" }
%"class.llvm::SmallVector.174" = type { %"class.llvm::SmallVectorImpl.175", %"struct.llvm::SmallVectorStorage.179" }
%"class.llvm::SmallVectorImpl.175" = type { %"class.llvm::SmallVectorTemplateBase.176" }
%"class.llvm::SmallVectorTemplateBase.176" = type { %"class.llvm::SmallVectorTemplateCommon.177" }
%"class.llvm::SmallVectorTemplateCommon.177" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.178" }
%"struct.llvm::AlignedCharArrayUnion.178" = type { %"struct.llvm::AlignedCharArray" }
%"struct.llvm::SmallVectorStorage.179" = type { [7 x %"struct.llvm::AlignedCharArrayUnion.178"] }
%"class.llvm::Recycler.180" = type { %"class.llvm::iplist.168" }
%"struct.llvm::ilist.181" = type { %"class.llvm::iplist.182" }
%"class.llvm::iplist.182" = type { %"struct.llvm::ilist_traits.183", %"class.llvm::MachineBasicBlock"* }
%"struct.llvm::ilist_traits.183" = type { %"class.llvm::ilist_half_node.1" }
%"class.llvm::ArrayRecycler<llvm::MachineOperand, 8>::Capacity" = type { i8 }
%"class.llvm::ConstantInt" = type { %"class.llvm::Constant", %"class.llvm::APInt" }
%"class.llvm::APInt" = type { i32, %union.anon.189 }
%union.anon.189 = type { i64 }
%"class.llvm::ConstantFP" = type { %"class.llvm::Constant", %"class.llvm::APFloat" }
%"class.llvm::APFloat" = type { %"struct.llvm::fltSemantics"*, %"union.llvm::APFloat::Significand", i16, i8 }
%"struct.llvm::fltSemantics" = type opaque
%"union.llvm::APFloat::Significand" = type { i64 }
%"class.llvm::BlockAddress" = type { %"class.llvm::Constant" }
%"class.llvm::hash_code" = type { i64 }
%"struct.llvm::hashing::detail::hash_combine_recursive_helper" = type { [64 x i8], %"struct.llvm::hashing::detail::hash_state", i64 }
%"struct.llvm::hashing::detail::hash_state" = type { i64, i64, i64, i64, i64, i64, i64, i64 }
%"class.llvm::PrintReg" = type { %"class.llvm::TargetRegisterInfo"*, i32, i32 }
%"class.llvm::PseudoSourceValue" = type { %"class.llvm::Value" }
%"class.llvm::FoldingSetNodeID" = type { %"class.llvm::SmallVector.194" }
%"class.llvm::SmallVector.194" = type { [28 x i8], %"struct.llvm::SmallVectorStorage.200" }
%"struct.llvm::SmallVectorStorage.200" = type { [31 x %"struct.llvm::AlignedCharArrayUnion.198"] }
%"struct.llvm::ArrayRecycler<llvm::MachineOperand, 8>::FreeList" = type { %"struct.llvm::ArrayRecycler<llvm::MachineOperand, 8>::FreeList"* }
%"class.llvm::ilist_iterator.202" = type { %"class.llvm::MachineInstr"* }
%"class.llvm::TargetInstrInfo" = type { i32 (...)**, [28 x i8], i32, i32 }
%"struct.std::pair.203" = type { i8, i8 }
%"class.llvm::SmallVectorImpl.195" = type { %"class.llvm::SmallVectorTemplateBase.196" }
%"class.llvm::SmallVectorTemplateBase.196" = type { %"class.llvm::SmallVectorTemplateCommon.197" }
%"class.llvm::SmallVectorTemplateCommon.197" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.198" }
%"class.llvm::AliasAnalysis" = type { i32 (...)**, %"class.llvm::DataLayout"*, %"class.llvm::TargetLibraryInfo"*, %"class.llvm::AliasAnalysis"* }
%"class.llvm::TargetLibraryInfo" = type opaque
%"struct.llvm::AliasAnalysis::Location" = type { %"class.llvm::Value"*, i64, %"class.llvm::MDNode"* }
%"class.llvm::DIVariable" = type { %"class.llvm::DIDescriptor" }
%"class.llvm::DIDescriptor" = type { %"class.llvm::MDNode"* }
%"class.llvm::DIScope" = type { %"class.llvm::DIDescriptor" }
%"class.llvm::ArrayRef.208" = type { i32*, i64 }
%"class.llvm::SmallVector.209" = type { %"class.llvm::SmallVectorImpl.210", %"struct.llvm::SmallVectorStorage.214" }
%"class.llvm::SmallVectorImpl.210" = type { %"class.llvm::SmallVectorTemplateBase.211" }
%"class.llvm::SmallVectorTemplateBase.211" = type { %"class.llvm::SmallVectorTemplateCommon.212" }
%"class.llvm::SmallVectorTemplateCommon.212" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.213" }
%"struct.llvm::AlignedCharArrayUnion.213" = type { %"struct.llvm::AlignedCharArray" }
%"struct.llvm::SmallVectorStorage.214" = type { [7 x %"struct.llvm::AlignedCharArrayUnion.213"] }
%"class.llvm::Twine" = type { %"union.llvm::Twine::Child", %"union.llvm::Twine::Child", i8, i8 }
%"union.llvm::Twine::Child" = type { %"class.llvm::Twine"* }
%"struct.std::random_access_iterator_tag" = type { i8 }

declare void @_ZN4llvm19MachineRegisterInfo27removeRegOperandFromUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"*, %"class.llvm::MachineOperand"*)

declare void @_ZN4llvm19MachineRegisterInfo22addRegOperandToUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"*, %"class.llvm::MachineOperand"*)

declare zeroext i32 @_ZNK4llvm14MCRegisterInfo9getSubRegEjj(%"class.llvm::MCRegisterInfo"*, i32 zeroext, i32 zeroext)

define void @_ZN4llvm14MachineOperand12substPhysRegEjRKNS_18TargetRegisterInfoE(%"class.llvm::MachineOperand"* %this, i32 zeroext %Reg, %"class.llvm::TargetRegisterInfo"* %TRI) align 2 {
entry:
  %SubReg_TargetFlags.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %this, i64 0, i32 1
  %0 = bitcast [3 x i8]* %SubReg_TargetFlags.i to i24*
  %bf.load.i = load i24, i24* %0, align 1
  %bf.lshr.i = lshr i24 %bf.load.i, 12
  %tobool = icmp eq i24 %bf.lshr.i, 0
  br i1 %tobool, label %if.end, label %if.then

if.then:                                          ; preds = %entry
  %bf.cast.i = zext i24 %bf.lshr.i to i32
  %add.ptr = getelementptr inbounds %"class.llvm::TargetRegisterInfo", %"class.llvm::TargetRegisterInfo"* %TRI, i64 0, i32 1
  %call3 = tail call zeroext i32 @_ZNK4llvm14MCRegisterInfo9getSubRegEjj(%"class.llvm::MCRegisterInfo"* %add.ptr, i32 zeroext %Reg, i32 zeroext %bf.cast.i)
  %bf.load.i10 = load i24, i24* %0, align 1
  %bf.clear.i = and i24 %bf.load.i10, 4095
  store i24 %bf.clear.i, i24* %0, align 1
  br label %if.end

if.end:                                           ; preds = %entry, %if.then
  %Reg.addr.0 = phi i32 [ %call3, %if.then ], [ %Reg, %entry ]
  %RegNo.i.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %this, i64 0, i32 2, i32 0
  %1 = load i32, i32* %RegNo.i.i, align 4
  %cmp.i = icmp eq i32 %1, %Reg.addr.0
  br i1 %cmp.i, label %_ZN4llvm14MachineOperand6setRegEj.exit, label %if.end.i

if.end.i:                                         ; preds = %if.end
  %ParentMI.i.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %this, i64 0, i32 3
  %2 = load %"class.llvm::MachineInstr"*, %"class.llvm::MachineInstr"** %ParentMI.i.i, align 8
  %tobool.i = icmp eq %"class.llvm::MachineInstr"* %2, null
  br i1 %tobool.i, label %if.end13.i, label %if.then3.i

if.then3.i:                                       ; preds = %if.end.i
  %Parent.i.i = getelementptr inbounds %"class.llvm::MachineInstr", %"class.llvm::MachineInstr"* %2, i64 0, i32 2
  %3 = load %"class.llvm::MachineBasicBlock"*, %"class.llvm::MachineBasicBlock"** %Parent.i.i, align 8
  %tobool5.i = icmp eq %"class.llvm::MachineBasicBlock"* %3, null
  br i1 %tobool5.i, label %if.end13.i, label %if.then6.i

if.then6.i:                                       ; preds = %if.then3.i
  %xParent.i.i = getelementptr inbounds %"class.llvm::MachineBasicBlock", %"class.llvm::MachineBasicBlock"* %3, i64 0, i32 4
  %4 = load %"class.llvm::MachineFunction"*, %"class.llvm::MachineFunction"** %xParent.i.i, align 8
  %tobool8.i = icmp eq %"class.llvm::MachineFunction"* %4, null
  br i1 %tobool8.i, label %if.end13.i, label %if.then9.i

if.then9.i:                                       ; preds = %if.then6.i
  %RegInfo.i.i = getelementptr inbounds %"class.llvm::MachineFunction", %"class.llvm::MachineFunction"* %4, i64 0, i32 5
  %5 = load %"class.llvm::MachineRegisterInfo"*, %"class.llvm::MachineRegisterInfo"** %RegInfo.i.i, align 8
  tail call void @_ZN4llvm19MachineRegisterInfo27removeRegOperandFromUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"* %5, %"class.llvm::MachineOperand"* %this)
  store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4
  tail call void @_ZN4llvm19MachineRegisterInfo22addRegOperandToUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"* %5, %"class.llvm::MachineOperand"* %this)
  br label %_ZN4llvm14MachineOperand6setRegEj.exit

if.end13.i:                                       ; preds = %if.then6.i, %if.then3.i, %if.end.i
  store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4
  br label %_ZN4llvm14MachineOperand6setRegEj.exit

_ZN4llvm14MachineOperand6setRegEj.exit:           ; preds = %if.end, %if.then9.i, %if.end13.i
  ret void
}

; CHECK-NOT: lbzu 3, 1(3)