llvm.org GIT mirror llvm / release_39 lib / Target / X86 / X86InstrXOP.td
release_39

Tree @release_39 (Download .tar.gz)

X86InstrXOP.td @release_39raw · history · blame

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes XOP (eXtended OPerations)
//
//===----------------------------------------------------------------------===//

multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
}

let ExeDomain = SSEPackedInt in {
  defm VPHSUBWD  : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>;
  defm VPHSUBDQ  : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>;
  defm VPHSUBBW  : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>;
  defm VPHADDWQ  : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>;
  defm VPHADDWD  : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>;
  defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>;
  defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>;
  defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>;
  defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>;
  defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>;
  defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>;
  defm VPHADDDQ  : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>;
  defm VPHADDBW  : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>;
  defm VPHADDBQ  : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>;
  defm VPHADDBD  : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>;
}

// Scalar load 2 addr operand instructions
multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
                     Operand memop, ComplexPattern mem_cpat> {
  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
}

multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
                     PatFrag memop> {
  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
}

multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
                     PatFrag memop> {
  def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
  def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
           [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
}

let ExeDomain = SSEPackedSingle in {
  defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
                           ssmem, sse_load_f32>;
  defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>;
  defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>;
}

let ExeDomain = SSEPackedDouble in {
  defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
                           sdmem, sse_load_f64>;
  defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>;
  defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>;
}

multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
                  ValueType vt128> {
  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
           (ins VR128:$src1, VR128:$src2),
           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
           XOP_4VOp3, Sched<[WriteVarVecShift]>;
  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
           (ins VR128:$src1, i128mem:$src2),
           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1),
                             (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
           XOP_4V, VEX_W, Sched<[WriteVarVecShift, ReadAfterLd]>;
  def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
           (ins i128mem:$src1, VR128:$src2),
           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
                             (vt128 VR128:$src2))))]>,
             XOP_4VOp3, Sched<[WriteVarVecShift, ReadAfterLd]>;
}

let ExeDomain = SSEPackedInt in {
  defm VPROTB : xop3op<0x90, "vprotb", X86vprot, v16i8>;
  defm VPROTD : xop3op<0x92, "vprotd", X86vprot, v4i32>;
  defm VPROTQ : xop3op<0x93, "vprotq", X86vprot, v2i64>;
  defm VPROTW : xop3op<0x91, "vprotw", X86vprot, v8i16>;
  defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>;
  defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>;
  defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>;
  defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>;
  defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>;
  defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>;
  defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>;
  defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>;
}

multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
                     ValueType vt128> {
  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
           (ins VR128:$src1, u8imm:$src2),
           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
           (ins i128mem:$src1, u8imm:$src2),
           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
}

let ExeDomain = SSEPackedInt in {
  defm VPROTB : xop3opimm<0xC0, "vprotb", X86vproti, v16i8>;
  defm VPROTD : xop3opimm<0xC2, "vprotd", X86vproti, v4i32>;
  defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vproti, v2i64>;
  defm VPROTW : xop3opimm<0xC1, "vprotw", X86vproti, v8i16>;
}

// Instruction where second source can be memory, but third must be register
multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
  let isCommutable = 1 in
  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
           (ins VR128:$src1, VR128:$src2, VR128:$src3),
           !strconcat(OpcodeStr,
           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
           [(set VR128:$dst,
              (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
           !strconcat(OpcodeStr,
           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
           [(set VR128:$dst,
              (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
              VR128:$src3))]>, XOP_4V, VEX_I8IMM;
}

let ExeDomain = SSEPackedInt in {
  defm VPMADCSWD  : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
  defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
  defm VPMACSWW   : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
  defm VPMACSWD   : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
  defm VPMACSSWW  : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
  defm VPMACSSWD  : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
  defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
  defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
  defm VPMACSSDD  : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
  defm VPMACSDQL  : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
  defm VPMACSDQH  : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
  defm VPMACSDD   : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
}

// Instruction where second source can be memory, third must be imm8
multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
  let isCommutable = 1 in
  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
           (ins VR128:$src1, VR128:$src2, XOPCC:$cc),
           !strconcat("vpcom${cc}", Suffix,
           "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
                             i8immZExt3:$cc)))]>,
           XOP_4V;
  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
           (ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
           !strconcat("vpcom${cc}", Suffix,
           "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
           [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1),
                             (vt128 (bitconvert (loadv2i64 addr:$src2))),
                              i8immZExt3:$cc)))]>,
           XOP_4V;
  let isAsmParserOnly = 1, hasSideEffects = 0 in {
    def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
                 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
                 !strconcat("vpcom", Suffix,
                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
                 []>, XOP_4V;
    let mayLoad = 1 in
    def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
                 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
                 !strconcat("vpcom", Suffix,
                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
                 []>, XOP_4V;
  }
}

let ExeDomain = SSEPackedInt in { // SSE integer instructions
  defm VPCOMB  : xopvpcom<0xCC, "b", X86vpcom, v16i8>;
  defm VPCOMW  : xopvpcom<0xCD, "w", X86vpcom, v8i16>;
  defm VPCOMD  : xopvpcom<0xCE, "d", X86vpcom, v4i32>;
  defm VPCOMQ  : xopvpcom<0xCF, "q", X86vpcom, v2i64>;
  defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8>;
  defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16>;
  defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32>;
  defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64>;
}

multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
                  ValueType vt128> {
  def rrr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, VR128:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
                             (vt128 VR128:$src3))))]>,
            XOP_4V, VEX_I8IMM;
  def rrm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, i128mem:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            [(set VR128:$dst,
              (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
                             (vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
            XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
  def rmr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
            (ins VR128:$src1, i128mem:$src2, VR128:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            [(set VR128:$dst,
              (v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
                             (vt128 VR128:$src3))))]>,
            XOP_4V, VEX_I8IMM;
  // For disassembler
  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
  def rrr_REV : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
                (ins VR128:$src1, VR128:$src2, VR128:$src3),
                !strconcat(OpcodeStr,
                "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
                []>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
}

let ExeDomain = SSEPackedInt in {
  defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8>;
}

// Instruction where either second or third source can be memory
multiclass xop4op_int<bits<8> opc, string OpcodeStr,
                      Intrinsic Int128, Intrinsic Int256> {
  // 128-bit Instruction
  def rrr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, VR128:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>,
            XOP_4V, VEX_I8IMM;
  def rrm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, i128mem:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            [(set VR128:$dst,
              (Int128 VR128:$src1, VR128:$src2,
               (bitconvert (loadv2i64 addr:$src3))))]>,
            XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
  def rmr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
            (ins VR128:$src1, i128mem:$src2, VR128:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            [(set VR128:$dst,
              (Int128 VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
               VR128:$src3))]>,
            XOP_4V, VEX_I8IMM;
  // For disassembler
  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
  def rrr_REV : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, VR128:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            []>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4;

  // 256-bit Instruction
  def rrrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
             (ins VR256:$src1, VR256:$src2, VR256:$src3),
             !strconcat(OpcodeStr,
             "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
             [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>,
             XOP_4V, VEX_I8IMM, VEX_L;
  def rrmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
             (ins VR256:$src1, VR256:$src2, i256mem:$src3),
             !strconcat(OpcodeStr,
             "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
             [(set VR256:$dst,
               (Int256 VR256:$src1, VR256:$src2,
               (bitconvert (loadv4i64 addr:$src3))))]>,
             XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
  def rmrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
             (ins VR256:$src1, f256mem:$src2, VR256:$src3),
             !strconcat(OpcodeStr,
             "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
             [(set VR256:$dst,
               (Int256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
                VR256:$src3))]>,
             XOP_4V, VEX_I8IMM, VEX_L;
  // For disassembler
  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
  def rrrY_REV : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
            (ins VR256:$src1, VR256:$src2, VR256:$src3),
            !strconcat(OpcodeStr,
            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
            []>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
}

let ExeDomain = SSEPackedInt in {
  defm VPCMOV : xop4op_int<0xA2, "vpcmov",
                           int_x86_xop_vpcmov, int_x86_xop_vpcmov_256>;
}

let Predicates = [HasXOP] in {
  def : Pat<(v2i64 (or (and VR128:$src3, VR128:$src1),
                       (X86andnp VR128:$src3, VR128:$src2))),
            (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;

  def : Pat<(v4i64 (or (and VR256:$src3, VR256:$src1),
                       (X86andnp VR256:$src3, VR256:$src2))),
            (VPCMOVrrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
}

multiclass xop5op<bits<8> opc, string OpcodeStr, SDNode OpNode,
                  ValueType vt128, ValueType vt256,
                  ValueType id128, ValueType id256,
                  PatFrag ld_128, PatFrag ld_256> {
  def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
        (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        [(set VR128:$dst,
           (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
                          (id128 VR128:$src3), (i8 imm:$src4))))]>;
  def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
        (ins VR128:$src1, VR128:$src2, i128mem:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        [(set VR128:$dst,
           (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
                          (id128 (bitconvert (loadv2i64 addr:$src3))),
                          (i8 imm:$src4))))]>,
        VEX_W, MemOp4;
  def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
        (ins VR128:$src1, f128mem:$src2, VR128:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        [(set VR128:$dst,
           (vt128 (OpNode (vt128 VR128:$src1),
                          (vt128 (bitconvert (ld_128 addr:$src2))),
                          (id128 VR128:$src3), (i8 imm:$src4))))]>;
  // For disassembler
  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
  def rr_REV : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
        (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        []>, VEX_W, MemOp4;

  def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
        (ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        [(set VR256:$dst,
           (vt256 (OpNode (vt256 VR256:$src1), (vt256 VR256:$src2),
                          (id256 VR256:$src3), (i8 imm:$src4))))]>, VEX_L;
  def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
        (ins VR256:$src1, VR256:$src2, i256mem:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        [(set VR256:$dst,
           (vt256 (OpNode (vt256 VR256:$src1), (vt256 VR256:$src2),
                          (id256 (bitconvert (loadv4i64 addr:$src3))),
                          (i8 imm:$src4))))]>, VEX_W, MemOp4, VEX_L;
  def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
        (ins VR256:$src1, f256mem:$src2, VR256:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        [(set VR256:$dst,
           (vt256 (OpNode (vt256 VR256:$src1),
                          (vt256 (bitconvert (ld_256 addr:$src2))),
                          (id256 VR256:$src3), (i8 imm:$src4))))]>, VEX_L;
  // For disassembler
  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
  def rrY_REV : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
        (ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
        !strconcat(OpcodeStr,
        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
        []>, VEX_W, MemOp4, VEX_L;
}

let ExeDomain = SSEPackedDouble in
  defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", X86vpermil2, v2f64, v4f64,
                           v2i64, v4i64, loadv2f64, loadv4f64>;

let ExeDomain = SSEPackedSingle in
  defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", X86vpermil2, v4f32, v8f32,
                           v4i32, v8i32, loadv4f32, loadv8f32>;