Tree @release_37 (Download .tar.gz)
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- 2006-11-10-CycleInDAG.ll
- 2007-01-19-InfiniteLoop.ll
- 2007-03-07-CombinerCrash.ll
- 2007-03-13-InstrSched.ll
- 2007-03-21-JoinIntervalsCrash.ll
- 2007-03-27-RegScavengerAssert.ll
- 2007-03-30-RegScavengerAssert.ll
- 2007-04-02-RegScavengerAssert.ll
- 2007-04-03-PEIBug.ll
- 2007-04-03-UndefinedSymbol.ll
- 2007-04-30-CombinerCrash.ll
- 2007-05-03-BadPostIndexedLd.ll
- 2007-05-07-tailmerge-1.ll
- 2007-05-09-tailmerge-2.ll
- 2007-05-14-InlineAsmCstCrash.ll
- 2007-05-14-RegScavengerAssert.ll
- 2007-05-22-tailmerge-3.ll
- 2007-05-23-BadPreIndexedStore.ll
- 2007-08-15-ReuseBug.ll
- 2008-02-04-LocalRegAllocBug.ll
- 2008-02-29-RegAllocLocal.ll
- 2008-03-05-SxtInRegBug.ll
- 2008-03-07-RegScavengerAssert.ll
- 2008-04-04-ScavengerAssert.ll
- 2008-04-10-ScavengerAssert.ll
- 2008-04-11-PHIofImpDef.ll
- 2008-05-19-LiveIntervalsBug.ll
- 2008-05-19-ScavengerAssert.ll
- 2008-07-17-Fdiv.ll
- 2008-07-24-CodeGenPrepCrash.ll
- 2008-08-07-AsmPrintBug.ll
- 2008-09-17-CoalescerBug.ll
- 2008-11-18-ScavengerAssert.ll
- 2009-02-16-SpillerBug.ll
- 2009-02-22-SoftenFloatVaArg.ll
- 2009-02-27-SpillerBug.ll
- 2009-03-07-SpillerBug.ll
- 2009-03-09-AddrModeBug.ll
- 2009-04-06-AsmModifier.ll
- 2009-04-08-AggregateAddr.ll
- 2009-04-08-FloatUndef.ll
- 2009-04-08-FREM.ll
- 2009-04-09-RegScavengerAsm.ll
- 2009-05-05-DAGCombineBug.ll
- 2009-05-07-RegAllocLocal.ll
- 2009-05-11-CodePlacementCrash.ll
- 2009-05-18-InlineAsmMem.ll
- 2009-06-02-ISelCrash.ll
- 2009-06-04-MissingLiveIn.ll
- 2009-06-15-RegScavengerAssert.ll
- 2009-06-19-RegScavengerAssert.ll
- 2009-06-22-CoalescerBug.ll
- 2009-06-30-RegScavengerAssert.ll
- 2009-06-30-RegScavengerAssert2.ll
- 2009-06-30-RegScavengerAssert3.ll
- 2009-06-30-RegScavengerAssert4.ll
- 2009-06-30-RegScavengerAssert5.ll
- 2009-07-01-CommuteBug.ll
- 2009-07-09-asm-p-constraint.ll
- 2009-07-18-RewriterBug.ll
- 2009-07-22-ScavengerAssert.ll
- 2009-07-22-SchedulerAssert.ll
- 2009-07-29-VFP3Registers.ll
- 2009-08-02-RegScavengerAssert-Neon.ll
- 2009-08-04-RegScavengerAssert-2.ll
- 2009-08-04-RegScavengerAssert.ll
- 2009-08-15-RegScavenger-EarlyClobber.ll
- 2009-08-15-RegScavengerAssert.ll
- 2009-08-21-PostRAKill.ll
- 2009-08-21-PostRAKill2.ll
- 2009-08-21-PostRAKill3.ll
- 2009-08-26-ScalarToVector.ll
- 2009-08-27-ScalarToVector.ll
- 2009-08-29-ExtractEltf32.ll
- 2009-08-29-TooLongSplat.ll
- 2009-08-31-LSDA-Name.ll
- 2009-08-31-TwoRegShuffle.ll
- 2009-09-09-AllOnes.ll
- 2009-09-09-fpcmp-ole.ll
- 2009-09-10-postdec.ll
- 2009-09-13-InvalidSubreg.ll
- 2009-09-13-InvalidSuperReg.ll
- 2009-09-20-LiveIntervalsBug.ll
- 2009-09-21-LiveVariablesBug.ll
- 2009-09-22-LiveVariablesBug.ll
- 2009-09-23-LiveVariablesBug.ll
- 2009-09-24-spill-align.ll
- 2009-09-27-CoalescerBug.ll
- 2009-09-28-LdStOptiBug.ll
- 2009-10-02-NEONSubregsBug.ll
- 2009-10-16-Scope.ll
- 2009-10-27-double-align.ll
- 2009-10-30.ll
- 2009-11-01-NeonMoves.ll
- 2009-11-02-NegativeLane.ll
- 2009-11-07-SubRegAsmPrinting.ll
- 2009-11-13-CoalescerCrash.ll
- 2009-11-13-ScavengerAssert.ll
- 2009-11-13-ScavengerAssert2.ll
- 2009-11-13-VRRewriterCrash.ll
- 2009-11-30-LiveVariablesBug.ll
- 2009-12-02-vtrn-undef.ll
- 2010-03-04-eabi-fp-spill.ll
- 2010-03-04-stm-undef-addr.ll
- 2010-03-18-ldm-rtrn.ll
- 2010-04-09-NeonSelect.ll
- 2010-04-13-v2f64SplitArg.ll
- 2010-04-14-SplitVector.ll
- 2010-04-15-ScavengerDebugValue.ll
- 2010-05-14-IllegalType.ll
- 2010-05-17-FastAllocCrash.ll
- 2010-05-18-LocalAllocCrash.ll
- 2010-05-18-PostIndexBug.ll
- 2010-05-19-Shuffles.ll
- 2010-05-20-NEONSpillCrash.ll
- 2010-05-21-BuildVector.ll
- 2010-06-11-vmovdrr-bitcast.ll
- 2010-06-21-LdStMultipleBug.ll
- 2010-06-21-nondarwin-tc.ll
- 2010-06-25-Thumb2ITInvalidIterator.ll
- 2010-06-29-PartialRedefFastAlloc.ll
- 2010-06-29-SubregImpDefs.ll
- 2010-07-26-GlobalMerge.ll
- 2010-08-04-EHCrash.ll
- 2010-08-04-StackVariable.ll
- 2010-09-21-OptCmpBug.ll
- 2010-10-25-ifcvt-ldm.ll
- 2010-11-15-SpillEarlyClobber.ll
- 2010-11-29-PrologueBug.ll
- 2010-12-07-PEIBug.ll
- 2010-12-08-tpsoft.ll
- 2010-12-15-elf-lcomm.ll
- 2010-12-17-LocalStackSlotCrash.ll
- 2011-01-19-MergedGlobalDbg.ll
- 2011-02-04-AntidepMultidef.ll
- 2011-02-07-AntidepClobber.ll
- 2011-03-10-DAGCombineCrash.ll
- 2011-03-15-LdStMultipleBug.ll
- 2011-03-23-PeepholeBug.ll
- 2011-04-07-schediv.ll
- 2011-04-11-MachineLICMBug.ll
- 2011-04-12-AlignBug.ll
- 2011-04-12-FastRegAlloc.ll
- 2011-04-15-AndVFlagPeepholeBug.ll
- 2011-04-15-RegisterCmpPeephole.ll
- 2011-04-26-SchedTweak.ll
- 2011-04-27-IfCvtBug.ll
- 2011-05-04-MultipleLandingPadSuccs.ll
- 2011-06-09-TailCallByVal.ll
- 2011-06-16-TailCallByVal.ll
- 2011-06-29-MergeGlobalsAlign.ll
- 2011-07-10-GlobalMergeBug.ll
- 2011-08-02-MergedGlobalDbg.ll
- 2011-08-12-vmovqqqq-pseudo.ll
- 2011-08-25-ldmia_ret.ll
- 2011-08-29-ldr_pre_imm.ll
- 2011-08-29-SchedCycle.ll
- 2011-09-09-OddVectorDivision.ll
- 2011-09-19-cpsr.ll
- 2011-09-28-CMovCombineBug.ll
- 2011-10-26-ExpandUnalignedLoadCrash.ll
- 2011-10-26-memset-inline.ll
- 2011-10-26-memset-with-neon.ll
- 2011-11-07-PromoteVectorLoadStore.ll
- 2011-11-09-BitcastVectorDouble.ll
- 2011-11-09-IllegalVectorFPIntConvert.ll
- 2011-11-14-EarlyClobber.ll
- 2011-11-28-DAGCombineBug.ll
- 2011-11-29-128bitArithmetics.ll
- 2011-11-30-MergeAlignment.ll
- 2011-12-14-machine-sink.ll
- 2011-12-19-sjlj-clobber.ll
- 2012-01-23-PostRA-LICM.ll
- 2012-01-24-RegSequenceLiveRange.ll
- 2012-01-26-CoalescerBug.ll
- 2012-01-26-CopyPropKills.ll
- 2012-02-01-CoalescerBug.ll
- 2012-03-05-FPSCR-bug.ll
- 2012-03-13-DAGCombineBug.ll
- 2012-03-26-FoldImmBug.ll
- 2012-04-02-TwoAddrInstrCrash.ll
- 2012-04-10-DAGCombine.ll
- 2012-04-24-SplitEHCriticalEdge.ll
- 2012-05-04-vmov.ll
- 2012-05-10-PreferVMOVtoVDUP32.ll
- 2012-05-29-TailDupBug.ll
- 2012-06-12-SchedMemLatency.ll
- 2012-08-04-DtripleSpillReload.ll
- 2012-08-08-legalize-unaligned.ll
- 2012-08-09-neon-extload.ll
- 2012-08-13-bfi.ll
- 2012-08-23-legalize-vmull.ll
- 2012-08-27-CopyPhysRegCrash.ll
- 2012-08-30-select.ll
- 2012-09-18-ARMv4ISelBug.ll
- 2012-09-25-InlineAsmScalarToVectorConv.ll
- 2012-09-25-InlineAsmScalarToVectorConv2.ll
- 2012-10-04-AAPCS-byval-align8.ll
- 2012-10-04-FixedFrame-vs-byval.ll
- 2012-10-04-LDRB_POST_IMM-Crash.ll
- 2012-10-18-PR14099-ByvalFrameAddress.ll
- 2012-11-14-subs_carry.ll
- 2013-01-21-PR14992.ll
- 2013-02-27-expand-vfma.ll
- 2013-04-05-Small-ByVal-Structs-PR15293.ll
- 2013-04-16-AAPCS-C4-vs-VFP.ll
- 2013-04-16-AAPCS-C5-vs-VFP.ll
- 2013-04-18-load-overlap-PR14824.ll
- 2013-04-21-AAPCS-VA-C.1.cp.ll
- 2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
- 2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
- 2013-05-05-IfConvertBug.ll
- 2013-05-07-ByteLoadSameAddress.ll
- 2013-05-13-AAPCS-byval-padding.ll
- 2013-05-13-AAPCS-byval-padding2.ll
- 2013-05-13-DAGCombiner-undef-mask.ll
- 2013-05-31-char-shift-crash.ll
- 2013-06-03-ByVal-2Kbytes.ll
- 2013-07-29-vector-or-combine.ll
- 2013-10-11-select-stalls.ll
- 2013-11-08-inline-asm-neon-array.ll
- 2014-01-09-pseudo_expand_implicit_reg.ll
- 2014-02-05-vfp-regs-after-stack.ll
- 2014-02-21-byval-reg-split-alignment.ll
- 2014-05-14-DwarfEHCrash.ll
- 2014-07-18-earlyclobber-str-post.ll
- 2014-08-04-muls-it.ll
- 2015-01-21-thumbv4t-ldstr-opt.ll
- a15-mla.ll
- a15-partial-update.ll
- a15-SD-dep.ll
- a15.ll
- aapcs-hfa-code.ll
- aapcs-hfa.ll
- addrmode.ll
- addrspacecast.ll
- adv-copy-opt.ll
- aggregate-padding.ll
- aliases.ll
- align.ll
- alloc-no-stack-realign.ll
- alloca.ll
- argaddr.ll
- arguments-nosplit-double.ll
- arguments-nosplit-i64.ll
- arguments.ll
- arguments2.ll
- arguments3.ll
- arguments4.ll
- arguments5.ll
- arguments6.ll
- arguments7.ll
- arguments8.ll
- arguments_f64_backfill.ll
- arm-abi-attr.ll
- arm-and-tst-peephole.ll
- arm-asm.ll
- arm-frameaddr.ll
- arm-interleaved-accesses.ll
- arm-modifier.ll
- arm-negative-stride.ll
- arm-returnaddr.ll
- arm-ttype-target2.ll
- arm32-round-conv.ll
- arm32-rounding.ll
- armv4.ll
- atomic-64bit.ll
- atomic-cmp.ll
- atomic-cmpxchg.ll
- atomic-load-store.ll
- atomic-op.ll
- atomic-ops-v8.ll
- atomicrmw_minmax.ll
- available_externally.ll
- avoid-cpsr-rmw.ll
- bfc.ll
- bfi.ll
- bfx.ll
- bic.ll
- bicZext.ll
- big-endian-eh-unwind.ll
- big-endian-neon-bitconv.ll
- big-endian-neon-extend.ll
- big-endian-neon-trunc-store.ll
- big-endian-ret-f64.ll
- big-endian-vector-callee.ll
- big-endian-vector-caller.ll
- bits.ll
- bswap-inline-asm.ll
- bswap16.ll
- build-attributes-encoding.s
- build-attributes.ll
- bx_fold.ll
- byval-align.ll
- byval_load_align.ll
- cache-intrinsic.ll
- call-noret-minsize.ll
- call-noret.ll
- call-tc.ll
- call.ll
- call_nolink.ll
- carry.ll
- clz.ll
- cmn.ll
- cmpxchg-idioms.ll
- cmpxchg-weak.ll
- coalesce-dbgvalue.ll
- coalesce-subregs.ll
- code-placement.ll
- combine-movc-sub.ll
- commute-movcc.ll
- compare-call.ll
- constant-islands.ll
- constantfp.ll
- constants.ll
- copy-cpsr.ll
- copy-paired-reg.ll
- crash-greedy-v6.ll
- crash-greedy.ll
- crash-O0.ll
- crash-shufflevector.ll
- crash.ll
- crc32.ll
- cse-call.ll
- cse-ldrlit.ll
- cse-libcalls.ll
- ctor_order.ll
- ctors_dtors.ll
- cttz.ll
- cttz_vector.ll
- dagcombine-anyexttozeroext.ll
- dagcombine-concatvector.ll
- darwin-eabi.ll
- data-in-code-annotations.ll
- dbg.ll
- DbgValueOtherTargets.test
- debug-frame-large-stack.ll
- debug-frame-no-debug.ll
- debug-frame-vararg.ll
- debug-frame.ll
- debug-info-arg.ll
- debug-info-blocks.ll
- debug-info-branch-folding.ll
- debug-info-d16-reg.ll
- debug-info-no-frame.ll
- debug-info-qreg.ll
- debug-info-s16-reg.ll
- debug-info-sreg2.ll
- debug-segmented-stacks.ll
- default-float-abi.ll
- deps-fix.ll
- disable-fp-elim.ll
- disable-tail-calls.ll
- div.ll
- divmod-eabi.ll
- divmod.ll
- domain-conv-vmovs.ll
- dwarf-eh.ll
- dwarf-unwind.ll
- dyn-stackalloc.ll
- eh-dispcont.ll
- eh-resume-darwin.ll
- ehabi-filters.ll
- ehabi-handlerdata-nounwind.ll
- ehabi-handlerdata.ll
- ehabi-no-landingpad.ll
- ehabi-unwind.ll
- ehabi.ll
- elf-lcomm-align.ll
- emit-big-cst.ll
- extload-knownzero.ll
- extloadi1.ll
- fabs-neon.ll
- fabss.ll
- fadds.ll
- fast-isel-align.ll
- fast-isel-binary.ll
- fast-isel-br-const.ll
- fast-isel-br-phi.ll
- fast-isel-call-multi-reg-return.ll
- fast-isel-call.ll
- fast-isel-cmp-imm.ll
- fast-isel-conversion.ll
- fast-isel-crash.ll
- fast-isel-crash2.ll
- fast-isel-deadcode.ll
- fast-isel-ext.ll
- fast-isel-fold.ll
- fast-isel-frameaddr.ll
- fast-isel-GEP-coalesce.ll
- fast-isel-icmp.ll
- fast-isel-indirectbr.ll
- fast-isel-inline-asm.ll
- fast-isel-intrinsic.ll
- fast-isel-ldr-str-arm.ll
- fast-isel-ldr-str-thumb-neg-index.ll
- fast-isel-ldrh-strh-arm.ll
- fast-isel-load-store-verify.ll
- fast-isel-mvn.ll
- fast-isel-pic.ll
- fast-isel-pred.ll
- fast-isel-redefinition.ll
- fast-isel-remat-same-constant.ll
- fast-isel-ret.ll
- fast-isel-select.ll
- fast-isel-shift-materialize.ll
- fast-isel-shifter.ll
- fast-isel-static.ll
- fast-isel-update-valuemap-for-extract.ll
- fast-isel-vaddd.ll
- fast-isel-vararg.ll
- fast-isel.ll
- fast-tail-call.ll
- fastcc-vfp.ll
- fastisel-gep-promote-before-add.ll
- fastisel-thumb-litpool.ll
- fcopysign.ll
- fdivs.ll
- fixunsdfdi.ll
- flag-crash.ll
- floorf.ll
- fmacs.ll
- fmdrr-fmrrd.ll
- fmscs.ll
- fmuls.ll
- fnattr-trap.ll
- fnegs.ll
- fnmacs.ll
- fnmscs.ll
- fnmul.ll
- fnmuls.ll
- fold-const.ll
- fold-stack-adjust.ll
- formal.ll
- fp-arg-shuffle.ll
- fp-fast.ll
- fp.ll
- fp16-promote.ll
- fp16.ll
- fp_convert.ll
- fparith.ll
- fpcmp-f64-neon-opt.ll
- fpcmp-opt.ll
- fpcmp.ll
- fpcmp_ueq.ll
- fpconsts.ll
- fpconv.ll
- fpmem.ll
- fpow.ll
- fpowi.ll
- fptoint.ll
- frame-register.ll
- fsubs.ll
- func-argpassing-endian.ll
- fusedMAC.ll
- ghc-tcreturn-lowered.ll
- global-merge-1.ll
- global-merge-addrspace.ll
- global-merge.ll
- globals.ll
- gpr-paired-spill-thumbinst.ll
- gpr-paired-spill.ll
- gv-stubs-crash.ll
- half.ll
- hardfloat_neon.ll
- hello.ll
- hfa-in-contiguous-registers.ll
- hidden-vis-2.ll
- hidden-vis-3.ll
- hidden-vis.ll
- hints.ll
- iabs.ll
- ifconv-kills.ll
- ifconv-regmask.ll
- ifcvt-branch-weight-bug.ll
- ifcvt-branch-weight.ll
- ifcvt-callback.ll
- ifcvt-dead-def.ll
- ifcvt-iter-indbr.ll
- ifcvt-regmask-noreturn.ll
- ifcvt1.ll
- ifcvt10.ll
- ifcvt11.ll
- ifcvt12.ll
- ifcvt2.ll
- ifcvt3.ll
- ifcvt4.ll
- ifcvt5.ll
- ifcvt6.ll
- ifcvt7.ll
- ifcvt8.ll
- ifcvt9.ll
- illegal-vector-bitcast.ll
- imm.ll
- indirect-hidden.ll
- indirect-reg-input.ll
- indirectbr-2.ll
- indirectbr-3.ll
- indirectbr.ll
- inline-diagnostics.ll
- inlineasm-64bit.ll
- inlineasm-global.ll
- inlineasm-imm-arm.ll
- inlineasm-ldr-pseudo.ll
- inlineasm-switch-mode-oneway-from-arm.ll
- inlineasm-switch-mode-oneway-from-thumb.ll
- inlineasm-switch-mode.ll
- inlineasm.ll
- inlineasm2.ll
- inlineasm3.ll
- inlineasm4.ll
- insn-sched1.ll
- int-to-fp.ll
- integer_insertelement.ll
- interrupt-attr.ll
- intrinsics-crypto.ll
- intrinsics-memory-barrier.ll
- intrinsics-overflow.ll
- intrinsics-v8.ll
- intrinsics.ll
- invalid-target.ll
- invoke-donothing-assert.ll
- isel-v8i32-crash.ll
- ispositive.ll
- jump-table-islands-split.ll
- jump-table-islands.ll
- jumptable-label.ll
- krait-cpu-div-attribute.ll
- large-stack.ll
- ldaex-stlex.ll
- ldm.ll
- ldr.ll
- ldr_ext.ll
- ldr_frame.ll
- ldr_post.ll
- ldr_pre.ll
- ldrd-memoper.ll
- ldrd.ll
- ldst-f32-2-i32.ll
- ldstrex-m.ll
- ldstrex.ll
- lit.local.cfg
- load-address-masked.ll
- load-global.ll
- load-store-flags.ll
- load.ll
- load_i1_select.ll
- log2_not_readnone.ll
- long-setcc.ll
- long.ll
- long_shift.ll
- longMAC.ll
- lsr-code-insertion.ll
- lsr-icmp-imm.ll
- lsr-scale-addr-mode.ll
- lsr-unfolded-offset.ll
- machine-cse-cmp.ll
- machine-licm.ll
- mature-mc-support.ll
- mem.ll
- memcpy-inline.ll
- memfunc.ll
- memset-inline.ll
- MergeConsecutiveStores.ll
- metadata-default.ll
- metadata-short-enums.ll
- metadata-short-wchar.ll
- minsize-imms.ll
- minsize-litpools.ll
- misched-copy-arm.ll
- mls.ll
- movcc-double.ll
- movt-movw-global.ll
- movt.ll
- mul.ll
- mul_const.ll
- mulhi.ll
- mult-alt-generic-arm.ll
- mvn.ll
- named-reg-alloc.ll
- named-reg-notareg.ll
- negative-offset.ll
- neon-fma.ll
- neon-spfp.ll
- neon-v8.1a.ll
- neon_arith1.ll
- neon_cmp.ll
- neon_div.ll
- neon_fpconv.ll
- neon_ld1.ll
- neon_ld2.ll
- neon_minmax.ll
- neon_shift.ll
- neon_spill.ll
- neon_vabs.ll
- nest-register.ll
- no-fpu.ll
- no-tail-call.ll
- none-macho-v4t.ll
- none-macho.ll
- noopt-dmb-v7.ll
- nop_concat_vectors.ll
- noreturn.ll
- null-streamer.ll
- opt-shuff-tstore.ll
- optimize-dmbs-v7.ll
- optselect-regclass.ll
- out-of-registers.ll
- pack.ll
- peephole-bitcast.ll
- phi.ll
- pic.ll
- popcnt.ll
- pr13249.ll
- PR15053.ll
- pr18364-movw.ll
- pr3502.ll
- preferred-align.ll
- prefetch.ll
- print-memb-operand.ll
- private.ll
- rbit.ll
- readcyclecounter.ll
- reg_sequence.ll
- regpair_hint_phys.ll
- ret0.ll
- ret_arg1.ll
- ret_arg2.ll
- ret_arg3.ll
- ret_arg4.ll
- ret_arg5.ll
- ret_f32_arg2.ll
- ret_f32_arg5.ll
- ret_f64_arg2.ll
- ret_f64_arg_reg_split.ll
- ret_f64_arg_split.ll
- ret_f64_arg_stack.ll
- ret_i128_arg2.ll
- ret_i64_arg2.ll
- ret_i64_arg3.ll
- ret_i64_arg_split.ll
- ret_sret_vector.ll
- ret_void.ll
- returned-ext.ll
- returned-trunc-tail-calls.ll
- rev.ll
- saxpy10-a9.ll
- sbfx.ll
- sched-it-debug-nodes.ll
- section-name.ll
- section.ll
- segmented-stacks-dynamic.ll
- segmented-stacks.ll
- select-imm.ll
- select-undef.ll
- select.ll
- select_xform.ll
- setcc-sentinals.ll
- setcc-type-mismatch.ll
- shifter_operand.ll
- shuffle.ll
- sincos.ll
- sjlj-prepare-critical-edge.ll
- sjljehprepare-lower-empty-struct.ll
- smml.ll
- smul.ll
- smulw.ll
- space-directive.ll
- special-reg-acore.ll
- special-reg-mcore.ll
- special-reg.ll
- spill-q.ll
- ssp-data-layout.ll
- stack-alignment.ll
- stack-frame.ll
- stack-protector-bmovpcb_call.ll
- stack_guard_remat.ll
- stackpointer.ll
- stm.ll
- str_post.ll
- str_pre-2.ll
- str_pre.ll
- str_trunc.ll
- struct-byval-frame-index.ll
- struct_byval.ll
- struct_byval_arm_t1_t2.ll
- sub-cmp-peephole.ll
- sub.ll
- subreg-remat.ll
- subtarget-features-long-calls.ll
- swift-atomics.ll
- swift-vldm.ll
- sxt_rot.ll
- t2-imm.ll
- t2abs-killflags.ll
- tail-call-weak.ll
- tail-call.ll
- tail-dup-kill-flags.ll
- tail-dup.ll
- tail-merge-branch-weight.ll
- tail-opts.ll
- taildup-branch-weight.ll
- test-sharedidx.ll
- this-return.ll
- thread_pointer.ll
- thumb-alignment.ll
- thumb-big-stack.ll
- thumb-litpool.ll
- thumb1-varalloc.ll
- thumb1_return_sequence.ll
- thumb2-it-block.ll
- thumb2-size-opt.ll
- thumb2-size-reduction-internal-flags.ll
- thumb_indirect_calls.ll
- tls-models.ll
- tls1.ll
- tls2.ll
- tls3.ll
- trap.ll
- trunc_ldr.ll
- truncstore-dag-combine.ll
- tst_teq.ll
- twoaddrinstr.ll
- uint64tof64.ll
- umulo-32.ll
- unaligned_load_store.ll
- unaligned_load_store_vector.ll
- undef-sext.ll
- undefined.ll
- unord.ll
- unsafe-fsub.ll
- unwind-init.ll
- uxt_rot.ll
- uxtb.ll
- v1-constant-fold.ll
- va_arg.ll
- vaba.ll
- vabd.ll
- vabs.ll
- vadd.ll
- vararg_no_start.ll
- varargs-spill-stack-align-nacl.ll
- vargs.ll
- vargs_align.ll
- vbits.ll
- vbsl-constant.ll
- vbsl.ll
- vceq.ll
- vcge.ll
- vcgt.ll
- vcnt.ll
- vcombine.ll
- vcvt-cost.ll
- vcvt-v8.ll
- vcvt.ll
- vcvt_combine.ll
- vdiv_combine.ll
- vdup.ll
- vector-DAGCombine.ll
- vector-extend-narrow.ll
- vector-load.ll
- vector-promotion.ll
- vector-spilling.ll
- vector-store.ll
- vext.ll
- vfcmp.ll
- vfloatintrinsics.ll
- vfp-libcalls.ll
- vfp-regs-dwarf.ll
- vfp.ll
- vget_lane.ll
- vhadd.ll
- vhsub.ll
- vicmp.ll
- vld1.ll
- vld2.ll
- vld3.ll
- vld4.ll
- vlddup.ll
- vldlane.ll
- vldm-liveness.ll
- vldm-sched-a9.ll
- vminmax.ll
- vminmaxnm.ll
- vmla.ll
- vmls.ll
- vmov.ll
- vmul.ll
- vneg.ll
- vpadal.ll
- vpadd.ll
- vpminmax.ll
- vqadd.ll
- vqdmul.ll
- vqshl.ll
- vqshrn.ll
- vqsub.ll
- vrec.ll
- vrev.ll
- vsel.ll
- vselect_imax.ll
- vshift.ll
- vshiftins.ll
- vshl.ll
- vshll.ll
- vshrn.ll
- vsra.ll
- vst1.ll
- vst2.ll
- vst3.ll
- vst4.ll
- vstlane.ll
- vsub.ll
- vtbl.ll
- vtrn.ll
- vuzp.ll
- vzip.ll
- warn-stack.ll
- weak.ll
- weak2.ll
- widen-vmovs.ll
- wrong-t2stmia-size-opt.ll
- zero-cycle-zero.ll
- zextload_demandedbits.ll
select_xform.ll @release_37 — raw · history · blame
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 | ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
; rdar://8662825
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
; ARM-LABEL: t1:
; ARM: suble r1, r1, #-2147483647
; ARM: mov r0, r1
; T2-LABEL: t1:
; T2: mvn r0, #-2147483648
; T2: addle r1, r0
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
%tmp3 = add i32 %tmp2, %b
ret i32 %tmp3
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; ARM-LABEL: t2:
; ARM: suble r1, r1, #10
; ARM: mov r0, r1
; T2-LABEL: t2:
; T2: suble r1, #10
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 10
%tmp3 = sub i32 %b, %tmp2
ret i32 %tmp3
}
define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
; ARM-LABEL: t3:
; ARM: andge r3, r3, r2
; ARM: mov r0, r3
; T2-LABEL: t3:
; T2: andge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
%z = select i1 %cond, i32 -1, i32 %x
%s = and i32 %z, %y
ret i32 %s
}
define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
; ARM-LABEL: t4:
; ARM: orrge r3, r3, r2
; ARM: mov r0, r3
; T2-LABEL: t4:
; T2: orrge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
%z = select i1 %cond, i32 0, i32 %x
%s = or i32 %z, %y
ret i32 %s
}
define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
entry:
; ARM-LABEL: t5:
; ARM-NOT: moveq
; ARM: orreq r2, r2, #1
; T2-LABEL: t5:
; T2-NOT: moveq
; T2: orreq r2, r2, #1
%tmp1 = icmp eq i32 %a, %b
%tmp2 = zext i1 %tmp1 to i32
%tmp3 = or i32 %tmp2, %c
ret i32 %tmp3
}
define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; ARM-LABEL: t6:
; ARM-NOT: movge
; ARM: eorlt r3, r3, r2
; T2-LABEL: t6:
; T2-NOT: movge
; T2: eorlt r3, r2
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %c, i32 0
%tmp2 = xor i32 %tmp1, %d
ret i32 %tmp2
}
define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
entry:
; ARM-LABEL: t7:
; ARM-NOT: lsleq
; ARM: andeq r2, r2, r2, lsl #1
; T2-LABEL: t7:
; T2-NOT: lsleq.w
; T2: andeq.w r2, r2, r2, lsl #1
%tmp1 = shl i32 %c, 1
%cond = icmp eq i32 %a, %b
%tmp2 = select i1 %cond, i32 %tmp1, i32 -1
%tmp3 = and i32 %c, %tmp2
ret i32 %tmp3
}
; Fold ORRri into movcc.
define i32 @t8(i32 %a, i32 %b) nounwind {
; ARM-LABEL: t8:
; ARM: cmp r0, r1
; ARM: orrge r0, r1, #1
; T2-LABEL: t8:
; T2: cmp r0, r1
; T2: orrge r0, r1, #1
%x = or i32 %b, 1
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %a, i32 %x
ret i32 %tmp1
}
; Fold ANDrr into movcc.
define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
; ARM-LABEL: t9:
; ARM: cmp r0, r1
; ARM: andge r0, r1, r2
; T2-LABEL: t9:
; T2: cmp r0, r1
; T2: andge.w r0, r1, r2
%x = and i32 %b, %c
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %a, i32 %x
ret i32 %tmp1
}
; Fold EORrs into movcc.
define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; ARM-LABEL: t10:
; ARM: cmp r0, r1
; ARM: eorge r0, r1, r2, lsl #7
; T2-LABEL: t10:
; T2: cmp r0, r1
; T2: eorge.w r0, r1, r2, lsl #7
%s = shl i32 %c, 7
%x = xor i32 %b, %s
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %a, i32 %x
ret i32 %tmp1
}
; Fold ORRri into movcc, reversing the condition.
define i32 @t11(i32 %a, i32 %b) nounwind {
; ARM-LABEL: t11:
; ARM: cmp r0, r1
; ARM: orrlt r0, r1, #1
; T2-LABEL: t11:
; T2: cmp r0, r1
; T2: orrlt r0, r1, #1
%x = or i32 %b, 1
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %x, i32 %a
ret i32 %tmp1
}
; Fold ADDri12 into movcc
define i32 @t12(i32 %a, i32 %b) nounwind {
; ARM-LABEL: t12:
; ARM: cmp r0, r1
; ARM: addge r0, r1,
; T2-LABEL: t12:
; T2: cmp r0, r1
; T2: addwge r0, r1, #3000
%x = add i32 %b, 3000
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %a, i32 %x
ret i32 %tmp1
}
; Handle frame index operands.
define void @pr13628() nounwind uwtable align 2 {
%x3 = alloca i8, i32 256, align 8
%x4 = load i8, i8* undef, align 1
%x5 = icmp ne i8 %x4, 0
%x6 = select i1 %x5, i8* %x3, i8* null
call void @bar(i8* %x6) nounwind
ret void
}
declare void @bar(i8*)
; Fold zext i1 into predicated add
define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
entry:
; ARM: t13
; ARM: cmp r1, #10
; ARM: addgt r0, r0, #1
; T2: t13
; T2: cmp r1, #10
; T2: addgt r0, #1
%cmp = icmp sgt i32 %a, 10
%conv = zext i1 %cmp to i32
%add = add i32 %conv, %c
ret i32 %add
}
; Fold sext i1 into predicated sub
define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
entry:
; ARM: t14
; ARM: cmp r1, #10
; ARM: subgt r0, r0, #1
; T2: t14
; T2: cmp r1, #10
; T2: subgt r0, #1
%cmp = icmp sgt i32 %a, 10
%conv = sext i1 %cmp to i32
%add = add i32 %conv, %c
ret i32 %add
}
; Do not fold the xor into the select
define i32 @t15(i32 %p) {
entry:
; ARM-LABEL: t15:
; ARM: mov [[REG:r[0-9]+]], #2
; ARM: cmp r0, #8
; ARM: movwgt [[REG:r[0-9]+]], #1
; ARM: eor r0, [[REG:r[0-9]+]], #1
; T2-LABEL: t15:
; T2: movs [[REG:r[0-9]+]], #2
; T2: cmp [[REG:r[0-9]+]], #8
; T2: it gt
; T2: movgt [[REG:r[0-9]+]], #1
; T2: eor r0, [[REG:r[0-9]+]], #1
%cmp = icmp sgt i32 %p, 8
%a = select i1 %cmp, i32 1, i32 2
%xor = xor i32 %a, 1
ret i32 %xor
}
define i32 @t16(i32 %x, i32 %y) {
entry:
; ARM-LABEL: t16:
; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
; T2-LABEL: t16:
; T2: ands r0, {{r[0-9]+}}
%cmp = icmp eq i32 %x, 0
%cond = select i1 %cmp, i32 5, i32 2
%cmp1 = icmp eq i32 %y, 0
%cond2 = select i1 %cmp1, i32 3, i32 4
%and = and i32 %cond2, %cond
ret i32 %and
}
define i32 @t17(i32 %x, i32 %y) #0 {
entry:
; ARM-LABEL: t17:
; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
; T2-LABEL: t17:
; T2: ands r0, {{r[0-9]+}}
%cmp = icmp eq i32 %x, -1
%cond = select i1 %cmp, i32 5, i32 2
%cmp1 = icmp eq i32 %y, -1
%cond2 = select i1 %cmp1, i32 3, i32 4
%and = and i32 %cond2, %cond
ret i32 %and
}
define i32 @t18(i32 %x, i32 %y) #0 {
entry:
; ARM-LABEL: t18:
; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
; T2-LABEL: t18:
; T2: and.w r0, {{r[0-9]+}}
%cmp = icmp ne i32 %x, 0
%cond = select i1 %cmp, i32 5, i32 2
%cmp1 = icmp ne i32 %x, -1
%cond2 = select i1 %cmp1, i32 3, i32 4
%and = and i32 %cond2, %cond
ret i32 %and
}
define i32 @t19(i32 %x, i32 %y) #0 {
entry:
; ARM-LABEL: t19:
; ARM: orr r0, {{r[0-9]+}}, {{r[0-9]+}}
; T2-LABEL: t19:
; T2: orrs r0, {{r[0-9]+}}
%cmp = icmp ne i32 %x, 0
%cond = select i1 %cmp, i32 5, i32 2
%cmp1 = icmp ne i32 %y, 0
%cond2 = select i1 %cmp1, i32 3, i32 4
%or = or i32 %cond2, %cond
ret i32 %or
}
define i32 @t20(i32 %x, i32 %y) #0 {
entry:
; ARM-LABEL: t20:
; ARM: orr r0, {{r[0-9]+}}, {{r[0-9]+}}
; T2-LABEL: t20:
; T2: orrs r0, {{r[0-9]+}}
%cmp = icmp ne i32 %x, -1
%cond = select i1 %cmp, i32 5, i32 2
%cmp1 = icmp ne i32 %y, -1
%cond2 = select i1 %cmp1, i32 3, i32 4
%or = or i32 %cond2, %cond
ret i32 %or
}
define <2 x i32> @t21(<2 x i32> %lhs, <2 x i32> %rhs) {
; CHECK-LABEL: t21:
; CHECK-NOT: eor
; CHECK: mvn
; CHECK-NOT: eor
%tst = icmp eq <2 x i32> %lhs, %rhs
%ntst = xor <2 x i1> %tst, <i1 1 , i1 undef>
%btst = sext <2 x i1> %ntst to <2 x i32>
ret <2 x i32> %btst
}
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