llvm.org GIT mirror llvm / release_37 lib / Target / Sparc / SparcInstrInfo.td
release_37

Tree @release_37 (Download .tar.gz)

SparcInstrInfo.td @release_37raw · history · blame

   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111
 112
 113
 114
 115
 116
 117
 118
 119
 120
 121
 122
 123
 124
 125
 126
 127
 128
 129
 130
 131
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148
 149
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160
 161
 162
 163
 164
 165
 166
 167
 168
 169
 170
 171
 172
 173
 174
 175
 176
 177
 178
 179
 180
 181
 182
 183
 184
 185
 186
 187
 188
 189
 190
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213
 214
 215
 216
 217
 218
 219
 220
 221
 222
 223
 224
 225
 226
 227
 228
 229
 230
 231
 232
 233
 234
 235
 236
 237
 238
 239
 240
 241
 242
 243
 244
 245
 246
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285
 286
 287
 288
 289
 290
 291
 292
 293
 294
 295
 296
 297
 298
 299
 300
 301
 302
 303
 304
 305
 306
 307
 308
 309
 310
 311
 312
 313
 314
 315
 316
 317
 318
 319
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332
 333
 334
 335
 336
 337
 338
 339
 340
 341
 342
 343
 344
 345
 346
 347
 348
 349
 350
 351
 352
 353
 354
 355
 356
 357
 358
 359
 360
 361
 362
 363
 364
 365
 366
 367
 368
 369
 370
 371
 372
 373
 374
 375
 376
 377
 378
 379
 380
 381
 382
 383
 384
 385
 386
 387
 388
 389
 390
 391
 392
 393
 394
 395
 396
 397
 398
 399
 400
 401
 402
 403
 404
 405
 406
 407
 408
 409
 410
 411
 412
 413
 414
 415
 416
 417
 418
 419
 420
 421
 422
 423
 424
 425
 426
 427
 428
 429
 430
 431
 432
 433
 434
 435
 436
 437
 438
 439
 440
 441
 442
 443
 444
 445
 446
 447
 448
 449
 450
 451
 452
 453
 454
 455
 456
 457
 458
 459
 460
 461
 462
 463
 464
 465
 466
 467
 468
 469
 470
 471
 472
 473
 474
 475
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494
 495
 496
 497
 498
 499
 500
 501
 502
 503
 504
 505
 506
 507
 508
 509
 510
 511
 512
 513
 514
 515
 516
 517
 518
 519
 520
 521
 522
 523
 524
 525
 526
 527
 528
 529
 530
 531
 532
 533
 534
 535
 536
 537
 538
 539
 540
 541
 542
 543
 544
 545
 546
 547
 548
 549
 550
 551
 552
 553
 554
 555
 556
 557
 558
 559
 560
 561
 562
 563
 564
 565
 566
 567
 568
 569
 570
 571
 572
 573
 574
 575
 576
 577
 578
 579
 580
 581
 582
 583
 584
 585
 586
 587
 588
 589
 590
 591
 592
 593
 594
 595
 596
 597
 598
 599
 600
 601
 602
 603
 604
 605
 606
 607
 608
 609
 610
 611
 612
 613
 614
 615
 616
 617
 618
 619
 620
 621
 622
 623
 624
 625
 626
 627
 628
 629
 630
 631
 632
 633
 634
 635
 636
 637
 638
 639
 640
 641
 642
 643
 644
 645
 646
 647
 648
 649
 650
 651
 652
 653
 654
 655
 656
 657
 658
 659
 660
 661
 662
 663
 664
 665
 666
 667
 668
 669
 670
 671
 672
 673
 674
 675
 676
 677
 678
 679
 680
 681
 682
 683
 684
 685
 686
 687
 688
 689
 690
 691
 692
 693
 694
 695
 696
 697
 698
 699
 700
 701
 702
 703
 704
 705
 706
 707
 708
 709
 710
 711
 712
 713
 714
 715
 716
 717
 718
 719
 720
 721
 722
 723
 724
 725
 726
 727
 728
 729
 730
 731
 732
 733
 734
 735
 736
 737
 738
 739
 740
 741
 742
 743
 744
 745
 746
 747
 748
 749
 750
 751
 752
 753
 754
 755
 756
 757
 758
 759
 760
 761
 762
 763
 764
 765
 766
 767
 768
 769
 770
 771
 772
 773
 774
 775
 776
 777
 778
 779
 780
 781
 782
 783
 784
 785
 786
 787
 788
 789
 790
 791
 792
 793
 794
 795
 796
 797
 798
 799
 800
 801
 802
 803
 804
 805
 806
 807
 808
 809
 810
 811
 812
 813
 814
 815
 816
 817
 818
 819
 820
 821
 822
 823
 824
 825
 826
 827
 828
 829
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839
 840
 841
 842
 843
 844
 845
 846
 847
 848
 849
 850
 851
 852
 853
 854
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871
 872
 873
 874
 875
 876
 877
 878
 879
 880
 881
 882
 883
 884
 885
 886
 887
 888
 889
 890
 891
 892
 893
 894
 895
 896
 897
 898
 899
 900
 901
 902
 903
 904
 905
 906
 907
 908
 909
 910
 911
 912
 913
 914
 915
 916
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930
 931
 932
 933
 934
 935
 936
 937
 938
 939
 940
 941
 942
 943
 944
 945
 946
 947
 948
 949
 950
 951
 952
 953
 954
 955
 956
 957
 958
 959
 960
 961
 962
 963
 964
 965
 966
 967
 968
 969
 970
 971
 972
 973
 974
 975
 976
 977
 978
 979
 980
 981
 982
 983
 984
 985
 986
 987
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the Sparc instructions in TableGen format.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//

include "SparcInstrFormats.td"

//===----------------------------------------------------------------------===//
// Feature predicates.
//===----------------------------------------------------------------------===//

// True when generating 32-bit code.
def Is32Bit : Predicate<"!Subtarget->is64Bit()">;

// True when generating 64-bit code. This also implies HasV9.
def Is64Bit : Predicate<"Subtarget->is64Bit()">;

// HasV9 - This predicate is true when the target processor supports V9
// instructions.  Note that the machine may be running in 32-bit mode.
def HasV9   : Predicate<"Subtarget->isV9()">,
              AssemblerPredicate<"FeatureV9">;

// HasNoV9 - This predicate is true when the target doesn't have V9
// instructions.  Use of this is just a hack for the isel not having proper
// costs for V8 instructions that are more expensive than their V9 ones.
def HasNoV9 : Predicate<"!Subtarget->isV9()">;

// HasVIS - This is true when the target processor has VIS extensions.
def HasVIS : Predicate<"Subtarget->isVIS()">,
             AssemblerPredicate<"FeatureVIS">;
def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
             AssemblerPredicate<"FeatureVIS2">;
def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
             AssemblerPredicate<"FeatureVIS3">;

// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;

// UseDeprecatedInsts - This predicate is true when the target processor is a
// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
// to use when appropriate.  In either of these cases, the instruction selector
// will pick deprecated instructions.
def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;

//===----------------------------------------------------------------------===//
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//

def simm11  : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;

def simm13  : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;

def LO10 : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
                                   MVT::i32);
}]>;

def HI22 : SDNodeXForm<imm, [{
  // Transformation function: shift the immediate value down into the low bits.
  return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
                                   MVT::i32);
}]>;

def SETHIimm : PatLeaf<(imm), [{
  return isShiftedUInt<22, 10>(N->getZExtValue());
}], HI22>;

// Addressing modes.
def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;

// Address operands
def SparcMEMrrAsmOperand : AsmOperandClass {
  let Name = "MEMrr";
  let ParserMethod = "parseMEMOperand";
}

def SparcMEMriAsmOperand : AsmOperandClass {
  let Name = "MEMri";
  let ParserMethod = "parseMEMOperand";
}

def MEMrr : Operand<iPTR> {
  let PrintMethod = "printMemOperand";
  let MIOperandInfo = (ops ptr_rc, ptr_rc);
  let ParserMatchClass = SparcMEMrrAsmOperand;
}
def MEMri : Operand<iPTR> {
  let PrintMethod = "printMemOperand";
  let MIOperandInfo = (ops ptr_rc, i32imm);
  let ParserMatchClass = SparcMEMriAsmOperand;
}

def TLSSym : Operand<iPTR>;

// Branch targets have OtherVT type.
def brtarget : Operand<OtherVT> {
  let EncoderMethod = "getBranchTargetOpValue";
}

def bprtarget : Operand<OtherVT> {
  let EncoderMethod = "getBranchPredTargetOpValue";
}

def bprtarget16 : Operand<OtherVT> {
  let EncoderMethod = "getBranchOnRegTargetOpValue";
}

def calltarget : Operand<i32> {
  let EncoderMethod = "getCallTargetOpValue";
  let DecoderMethod = "DecodeCall";
}

def simm13Op : Operand<i32> {
  let DecoderMethod = "DecodeSIMM13";
}

// Operand for printing out a condition code.
let PrintMethod = "printCCOperand" in
  def CCOp : Operand<i32>;

def SDTSPcmpicc :
SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
def SDTSPcmpfcc :
SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
def SDTSPbrcc :
SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
def SDTSPselectcc :
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
def SDTSPFTOI :
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
def SDTSPFTOX :
SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
def SDTSPXTOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;

def SDTSPtlsadd :
SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
def SDTSPtlsld :
SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;

def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;

def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;

def SPftoi  : SDNode<"SPISD::FTOI", SDTSPFTOI>;
def SPitof  : SDNode<"SPISD::ITOF", SDTSPITOF>;
def SPftox  : SDNode<"SPISD::FTOX", SDTSPFTOX>;
def SPxtof  : SDNode<"SPISD::XTOF", SDTSPXTOF>;

def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;

//  These are target-independent nodes, but have target-specific formats.
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
def SDT_SPCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
                                        SDTCisVT<1, i32> ]>;

def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
                           [SDNPHasChain, SDNPOutGlue]>;
def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;

def SDT_SPCall    : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
def call          : SDNode<"SPISD::CALL", SDT_SPCall,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                            SDNPVariadic]>;

def SDT_SPRet     : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def retflag       : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;

def flushw        : SDNode<"SPISD::FLUSHW", SDTNone,
                           [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;

def tlsadd        : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
def tlsld         : SDNode<"SPISD::TLS_LD",  SDTSPtlsld>;
def tlscall       : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                             SDNPVariadic]>;

def getPCX        : Operand<iPTR> {
  let PrintMethod = "printGetPCX";
}

//===----------------------------------------------------------------------===//
// SPARC Flag Conditions
//===----------------------------------------------------------------------===//

// Note that these values must be kept in sync with the CCOp::CondCode enum
// values.
class ICC_VAL<int N> : PatLeaf<(i32 N)>;
def ICC_NE  : ICC_VAL< 9>;  // Not Equal
def ICC_E   : ICC_VAL< 1>;  // Equal
def ICC_G   : ICC_VAL<10>;  // Greater
def ICC_LE  : ICC_VAL< 2>;  // Less or Equal
def ICC_GE  : ICC_VAL<11>;  // Greater or Equal
def ICC_L   : ICC_VAL< 3>;  // Less
def ICC_GU  : ICC_VAL<12>;  // Greater Unsigned
def ICC_LEU : ICC_VAL< 4>;  // Less or Equal Unsigned
def ICC_CC  : ICC_VAL<13>;  // Carry Clear/Great or Equal Unsigned
def ICC_CS  : ICC_VAL< 5>;  // Carry Set/Less Unsigned
def ICC_POS : ICC_VAL<14>;  // Positive
def ICC_NEG : ICC_VAL< 6>;  // Negative
def ICC_VC  : ICC_VAL<15>;  // Overflow Clear
def ICC_VS  : ICC_VAL< 7>;  // Overflow Set

class FCC_VAL<int N> : PatLeaf<(i32 N)>;
def FCC_U   : FCC_VAL<23>;  // Unordered
def FCC_G   : FCC_VAL<22>;  // Greater
def FCC_UG  : FCC_VAL<21>;  // Unordered or Greater
def FCC_L   : FCC_VAL<20>;  // Less
def FCC_UL  : FCC_VAL<19>;  // Unordered or Less
def FCC_LG  : FCC_VAL<18>;  // Less or Greater
def FCC_NE  : FCC_VAL<17>;  // Not Equal
def FCC_E   : FCC_VAL<25>;  // Equal
def FCC_UE  : FCC_VAL<24>;  // Unordered or Equal
def FCC_GE  : FCC_VAL<25>;  // Greater or Equal
def FCC_UGE : FCC_VAL<26>;  // Unordered or Greater or Equal
def FCC_LE  : FCC_VAL<27>;  // Less or Equal
def FCC_ULE : FCC_VAL<28>;  // Unordered or Less or Equal
def FCC_O   : FCC_VAL<29>;  // Ordered

//===----------------------------------------------------------------------===//
// Instruction Class Templates
//===----------------------------------------------------------------------===//

/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
                 RegisterClass RC, ValueType Ty, Operand immOp> {
  def rr  : F3_1<2, Op3Val,
                 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
                 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
                 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
  def ri  : F3_2<2, Op3Val,
                 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
                 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
                 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
}

/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
/// pattern.
multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
  def rr  : F3_1<2, Op3Val,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
  def ri  : F3_2<2, Op3Val,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
}

// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
           RegisterClass RC, ValueType Ty> {
  def rr  : F3_1<3, Op3Val,
                 (outs RC:$dst), (ins MEMrr:$addr),
                 !strconcat(OpcStr, " [$addr], $dst"),
                 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
  def ri  : F3_2<3, Op3Val,
                 (outs RC:$dst), (ins MEMri:$addr),
                 !strconcat(OpcStr, " [$addr], $dst"),
                 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
}

// LoadA multiclass - As above, but also define alternate address space variant
multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
                 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
             Load<OpcStr, Op3Val, OpNode, RC, Ty> {
  // TODO: The LD*Arr instructions are currently asm only; hooking up
  // CodeGen's address spaces to use these is a future task.
  def Arr  : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
                !strconcat(OpcStr, "a [$addr] $asi, $dst"),
                []>;
}

// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
           RegisterClass RC, ValueType Ty> {
  def rr  : F3_1<3, Op3Val,
                 (outs), (ins MEMrr:$addr, RC:$rd),
                 !strconcat(OpcStr, " $rd, [$addr]"),
                 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
  def ri  : F3_2<3, Op3Val,
                 (outs), (ins MEMri:$addr, RC:$rd),
                 !strconcat(OpcStr, " $rd, [$addr]"),
                 [(OpNode Ty:$rd, ADDRri:$addr)]>;
}

multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
             Store<OpcStr, Op3Val, OpNode, RC, Ty> {
  // TODO: The ST*Arr instructions are currently asm only; hooking up
  // CodeGen's address spaces to use these is a future task.
  def Arr  : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
                  !strconcat(OpcStr, "a $rd, [$addr] $asi"),
                  []>;
}

//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//

// Pseudo instructions.
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSP<outs, ins, asmstr, pattern> {
  let isCodeGenOnly = 1;
  let isPseudo = 1;
}

// GETPCX for PIC
let Defs = [O7] in {
  def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
}

let Defs = [O6], Uses = [O6] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
                               "!ADJCALLSTACKDOWN $amt",
                               [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                            "!ADJCALLSTACKUP $amt1",
                            [(callseq_end timm:$amt1, timm:$amt2)]>;
}

let hasSideEffects = 1, mayStore = 1 in {
  let rd = 0, rs1 = 0, rs2 = 0 in
    def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
                      "flushw",
                      [(flushw)]>, Requires<[HasV9]>;
  let rd = 0, rs1 = 1, simm13 = 3 in
    def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
                   "ta 3",
                   [(flushw)]>;
}

// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
// instruction selection into a branch sequence.  This has to handle all
// permutations of selection between i32/f32/f64 on ICC and FCC.
// Expanded after instruction selection.
let Uses = [ICC], usesCustomInserter = 1 in {
  def SELECT_CC_Int_ICC
   : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
            "; SELECT_CC_Int_ICC PSEUDO!",
            [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
  def SELECT_CC_FP_ICC
   : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
            "; SELECT_CC_FP_ICC PSEUDO!",
            [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;

  def SELECT_CC_DFP_ICC
   : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
            "; SELECT_CC_DFP_ICC PSEUDO!",
            [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;

  def SELECT_CC_QFP_ICC
   : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
            "; SELECT_CC_QFP_ICC PSEUDO!",
            [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
}

let usesCustomInserter = 1, Uses = [FCC0] in {

  def SELECT_CC_Int_FCC
   : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
            "; SELECT_CC_Int_FCC PSEUDO!",
            [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;

  def SELECT_CC_FP_FCC
   : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
            "; SELECT_CC_FP_FCC PSEUDO!",
            [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
  def SELECT_CC_DFP_FCC
   : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
            "; SELECT_CC_DFP_FCC PSEUDO!",
            [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
  def SELECT_CC_QFP_FCC
   : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
            "; SELECT_CC_QFP_FCC PSEUDO!",
            [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
}

// Section B.1 - Load Integer Instructions, p. 90
let DecoderMethod = "DecodeLoadInt" in {
  defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
  defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
  defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
  defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
  defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
}

// Section B.2 - Load Floating-point Instructions, p. 92
let DecoderMethod = "DecodeLoadFP" in
  defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
let DecoderMethod = "DecodeLoadDFP" in
  defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
let DecoderMethod = "DecodeLoadQFP" in
  defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
               Requires<[HasV9, HasHardQuad]>;

// Section B.4 - Store Integer Instructions, p. 95
let DecoderMethod = "DecodeStoreInt" in {
  defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
  defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
  defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
}

// Section B.5 - Store Floating-point Instructions, p. 97
let DecoderMethod = "DecodeStoreFP" in
  defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
let DecoderMethod = "DecodeStoreDFP" in
  defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
let DecoderMethod = "DecodeStoreQFP" in
  defm STQF  : Store<"stq", 0b100110, store,         QFPRegs, f128>,
               Requires<[HasV9, HasHardQuad]>;

// Section B.8 - SWAP Register with Memory Instruction
// (Atomic swap)
let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
  def SWAPrr : F3_1<3, 0b001111,
                 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
                 "swap [$addr], $dst",
                 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
  def SWAPri : F3_2<3, 0b001111,
                 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
                 "swap [$addr], $dst",
                 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
  def SWAPArr : F3_1_asi<3, 0b011111,
                 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
                 "swapa [$addr] $asi, $dst",
                 [/*FIXME: pattern?*/]>;
}


// Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100,
                 (outs IntRegs:$rd), (ins i32imm:$imm22),
                 "sethi $imm22, $rd",
                 [(set i32:$rd, SETHIimm:$imm22)]>;

// Section B.10 - NOP Instruction, p. 105
// (It's a special case of SETHI)
let rd = 0, imm22 = 0 in
  def NOP : F2_1<0b100, (outs), (ins), "nop", []>;

// Section B.11 - Logical Instructions, p. 106
defm AND    : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;

def ANDNrr  : F3_1<2, 0b000101,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                   "andn $rs1, $rs2, $rd",
                   [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
def ANDNri  : F3_2<2, 0b000101,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                   "andn $rs1, $simm13, $rd", []>;

defm OR     : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;

def ORNrr   : F3_1<2, 0b000110,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                   "orn $rs1, $rs2, $rd",
                   [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
def ORNri   : F3_2<2, 0b000110,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                   "orn $rs1, $simm13, $rd", []>;
defm XOR    : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;

def XNORrr  : F3_1<2, 0b000111,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                   "xnor $rs1, $rs2, $rd",
                   [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
def XNORri  : F3_2<2, 0b000111,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                   "xnor $rs1, $simm13, $rd", []>;

let Defs = [ICC] in {
  defm ANDCC  : F3_12np<"andcc",  0b010001>;
  defm ANDNCC : F3_12np<"andncc", 0b010101>;
  defm ORCC   : F3_12np<"orcc",   0b010010>;
  defm ORNCC  : F3_12np<"orncc",  0b010110>;
  defm XORCC  : F3_12np<"xorcc",  0b010011>;
  defm XNORCC : F3_12np<"xnorcc", 0b010111>;
}

// Section B.12 - Shift Instructions, p. 107
defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;

// Section B.13 - Add Instructions, p. 108
defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;

// "LEA" forms of add (patterns to make tblgen happy)
let Predicates = [Is32Bit], isCodeGenOnly = 1 in
  def LEA_ADDri   : F3_2<2, 0b000000,
                     (outs IntRegs:$dst), (ins MEMri:$addr),
                     "add ${addr:arith}, $dst",
                     [(set iPTR:$dst, ADDRri:$addr)]>;

let Defs = [ICC] in
  defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;

let Uses = [ICC] in
  defm ADDC   : F3_12np<"addx", 0b001000>;

let Uses = [ICC], Defs = [ICC] in
  defm ADDE  : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;

// Section B.15 - Subtract Instructions, p. 110
defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, simm13Op>;
let Uses = [ICC], Defs = [ICC] in
  defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;

let Defs = [ICC] in
  defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;

let Uses = [ICC] in
  defm SUBC   : F3_12np <"subx", 0b001100>;

// cmp (from Section A.3) is a specialized alias for subcc
let Defs = [ICC], rd = 0 in {
  def CMPrr   : F3_1<2, 0b010100,
                     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
                     "cmp $rs1, $rs2",
                     [(SPcmpicc i32:$rs1, i32:$rs2)]>;
  def CMPri   : F3_2<2, 0b010100,
                     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
                     "cmp $rs1, $simm13",
                     [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
}

// Section B.18 - Multiply Instructions, p. 113
let Defs = [Y] in {
  defm UMUL : F3_12np<"umul", 0b001010>;
  defm SMUL : F3_12  <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
}

let Defs = [Y, ICC] in {
  defm UMULCC : F3_12np<"umulcc", 0b011010>;
  defm SMULCC : F3_12np<"smulcc", 0b011011>;
}

// Section B.19 - Divide Instructions, p. 115
let Uses = [Y], Defs = [Y] in {
  defm UDIV : F3_12np<"udiv", 0b001110>;
  defm SDIV : F3_12np<"sdiv", 0b001111>;
}

let Uses = [Y], Defs = [Y, ICC] in {
  defm UDIVCC : F3_12np<"udivcc", 0b011110>;
  defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
}

// Section B.20 - SAVE and RESTORE, p. 117
defm SAVE    : F3_12np<"save"   , 0b111100>;
defm RESTORE : F3_12np<"restore", 0b111101>;

// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119

// unconditional branch class.
class BranchAlways<dag ins, string asmstr, list<dag> pattern>
  : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
  let isBranch     = 1;
  let isTerminator = 1;
  let hasDelaySlot = 1;
  let isBarrier    = 1;
}

let cond = 8 in
  def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;


let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {

// conditional branch class:
class BranchSP<dag ins, string asmstr, list<dag> pattern>
 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;

// conditional branch with annul class:
class BranchSPA<dag ins, string asmstr, list<dag> pattern>
 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;

// Conditional branch class on %icc|%xcc with predication:
multiclass IPredBranch<string regstr, list<dag> CCPattern> {
  def CC    : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
                  !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
                   CCPattern>;
  def CCA   : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
                  !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
                   []>;
  def CCNT  : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
                   !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
                   []>;
  def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
                   !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
                   []>;
}

} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1


// Indirect branch instructions.
let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1, isBranch =1,
     isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
  def BINDrr  : F3_1<2, 0b111000,
                   (outs), (ins MEMrr:$ptr),
                   "jmp $ptr",
                   [(brind ADDRrr:$ptr)]>;
  def BINDri  : F3_2<2, 0b111000,
                   (outs), (ins MEMri:$ptr),
                   "jmp $ptr",
                   [(brind ADDRri:$ptr)]>;
}

let Uses = [ICC] in {
  def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
                         "b$cond $imm22",
                        [(SPbricc bb:$imm22, imm:$cond)]>;
  def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
                         "b$cond,a $imm22", []>;

  let Predicates = [HasV9], cc = 0b00 in
    defm BPI : IPredBranch<"%icc", []>;
}

// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121

let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {

// floating-point conditional branch class:
class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;

// floating-point conditional branch with annul class:
class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
 : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;

// Conditional branch class on %fcc0-%fcc3 with predication:
multiclass FPredBranch {
  def CC    : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
                                         FCCRegs:$cc),
                  "fb$cond $cc, $imm19", []>;
  def CCA   : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
                                         FCCRegs:$cc),
                  "fb$cond,a $cc, $imm19", []>;
  def CCNT  : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
                                         FCCRegs:$cc),
                  "fb$cond,pn $cc, $imm19", []>;
  def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
                                         FCCRegs:$cc),
                  "fb$cond,a,pn $cc, $imm19", []>;
}
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1

let Uses = [FCC0] in {
  def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
                              "fb$cond $imm22",
                              [(SPbrfcc bb:$imm22, imm:$cond)]>;
  def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
                             "fb$cond,a $imm22", []>;
}

let Predicates = [HasV9] in
  defm BPF : FPredBranch;


// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O6],
    hasDelaySlot = 1, isCall = 1 in {
  def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
                    "call $disp", []> {
    bits<30> disp;
    let op = 1;
    let Inst{29-0} = disp;
  }

  // indirect calls: special cases of JMPL.
  let isCodeGenOnly = 1, rd = 15 in {
    def CALLrr : F3_1<2, 0b111000,
                      (outs), (ins MEMrr:$ptr, variable_ops),
                      "call $ptr",
                      [(call ADDRrr:$ptr)]>;
    def CALLri : F3_2<2, 0b111000,
                      (outs), (ins MEMri:$ptr, variable_ops),
                      "call $ptr",
                      [(call ADDRri:$ptr)]>;
  }
}

// Section B.25 - Jump and Link Instruction

// JMPL Instruction.
let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
    DecoderMethod = "DecodeJMPL" in {
  def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
                  "jmpl $addr, $dst", []>;
  def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
                  "jmpl $addr, $dst", []>;
}

// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
    isCodeGenOnly = 1 in {
  let rd = 0, rs1 = 15 in
    def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
                   "jmp %o7+$val", [(retflag simm13:$val)]>;

  let rd = 0, rs1 = 31 in
    def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
                  "jmp %i7+$val", []>;
}

// Section B.26 - Return from Trap Instruction
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
     isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
  def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
                       "rett $addr", []>;
  def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
                       "rett $addr", []>;
}


// Section B.27 - Trap on Integer Condition Codes Instruction
multiclass TRAP<string regStr> {
  def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
                                       CCOp:$cond),
              !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
  def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
                                      CCOp:$cond),
              !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
}

let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
  defm TICC : TRAP<"%icc">;

let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
  def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;

// Section B.28 - Read State Register Instructions
let rs2 = 0 in
  def RDASR : F3_1<2, 0b101000,
                 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
                 "rd $rs1, $rd", []>;

// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
let Predicates = [HasNoV9] in {
  let rs2 = 0, rs1 = 0, Uses=[PSR] in
    def RDPSR : F3_1<2, 0b101001,
		     (outs IntRegs:$rd), (ins),
		     "rd %psr, $rd", []>;

  let rs2 = 0, rs1 = 0, Uses=[WIM] in
    def RDWIM : F3_1<2, 0b101010,
		     (outs IntRegs:$rd), (ins),
		     "rd %wim, $rd", []>;

  let rs2 = 0, rs1 = 0, Uses=[TBR] in
    def RDTBR : F3_1<2, 0b101011,
		     (outs IntRegs:$rd), (ins),
		     "rd %tbr, $rd", []>;
}

// Section B.29 - Write State Register Instructions
def WRASRrr : F3_1<2, 0b110000,
                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                 "wr $rs1, $rs2, $rd", []>;
def WRASRri : F3_2<2, 0b110000,
                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                 "wr $rs1, $simm13, $rd", []>;

// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
let Predicates = [HasNoV9] in {
  let Defs = [PSR], rd=0 in {
    def WRPSRrr : F3_1<2, 0b110001,
		     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
		     "wr $rs1, $rs2, %psr", []>;
    def WRPSRri : F3_2<2, 0b110001,
		     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
		     "wr $rs1, $simm13, %psr", []>;
  }

  let Defs = [WIM], rd=0 in {
    def WRWIMrr : F3_1<2, 0b110010,
		     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
		     "wr $rs1, $rs2, %wim", []>;
    def WRWIMri : F3_2<2, 0b110010,
		     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
		     "wr $rs1, $simm13, %wim", []>;
  }

  let Defs = [TBR], rd=0 in {
    def WRTBRrr : F3_1<2, 0b110011,
		     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
		     "wr $rs1, $rs2, %tbr", []>;
    def WRTBRri : F3_2<2, 0b110011,
		     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
		     "wr $rs1, $simm13, %tbr", []>;
  }
}

// Section B.30 - STBAR Instruction
let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
  def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;


// Section B.31 - Unimplmented Instruction
let rd = 0 in
  def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
                  "unimp $imm22", []>;

// Section B.32 - Flush Instruction Memory
let rd = 0 in {
  def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
                       "flush $addr", []>;
  def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
                       "flush $addr", []>;

  // The no-arg FLUSH is only here for the benefit of the InstAlias
  // "flush", which cannot seem to use FLUSHrr, due to the inability
  // to construct a MEMrr with fixed G0 registers.
  let rs1 = 0, rs2 = 0 in
    def FLUSH   : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
}

// Section B.33 - Floating-point Operate (FPop) Instructions

// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3u<2, 0b110100, 0b011000100,
                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
                 "fitos $rs2, $rd",
                 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
def FITOD : F3_3u<2, 0b110100, 0b011001000,
                 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
                 "fitod $rs2, $rd",
                 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
def FITOQ : F3_3u<2, 0b110100, 0b011001100,
                 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
                 "fitoq $rs2, $rd",
                 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
                 Requires<[HasHardQuad]>;

// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3u<2, 0b110100, 0b011010001,
                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
                 "fstoi $rs2, $rd",
                 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
def FDTOI : F3_3u<2, 0b110100, 0b011010010,
                 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
                 "fdtoi $rs2, $rd",
                 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
def FQTOI : F3_3u<2, 0b110100, 0b011010011,
                 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
                 "fqtoi $rs2, $rd",
                 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
                 Requires<[HasHardQuad]>;

// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3u<2, 0b110100, 0b011001001,
                 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
                 "fstod $rs2, $rd",
                 [(set f64:$rd, (fextend f32:$rs2))]>;
def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
                 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
                 "fstoq $rs2, $rd",
                 [(set f128:$rd, (fextend f32:$rs2))]>,
                 Requires<[HasHardQuad]>;
def FDTOS : F3_3u<2, 0b110100, 0b011000110,
                 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
                 "fdtos $rs2, $rd",
                 [(set f32:$rd, (fround f64:$rs2))]>;
def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
                 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
                 "fdtoq $rs2, $rd",
                 [(set f128:$rd, (fextend f64:$rs2))]>,
                 Requires<[HasHardQuad]>;
def FQTOS : F3_3u<2, 0b110100, 0b011000111,
                 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
                 "fqtos $rs2, $rd",
                 [(set f32:$rd, (fround f128:$rs2))]>,
                 Requires<[HasHardQuad]>;
def FQTOD : F3_3u<2, 0b110100, 0b011001011,
                 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
                 "fqtod $rs2, $rd",
                 [(set f64:$rd, (fround f128:$rs2))]>,
                 Requires<[HasHardQuad]>;

// Floating-point Move Instructions, p. 144
def FMOVS : F3_3u<2, 0b110100, 0b000000001,
                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
                 "fmovs $rs2, $rd", []>;
def FNEGS : F3_3u<2, 0b110100, 0b000000101,
                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
                 "fnegs $rs2, $rd",
                 [(set f32:$rd, (fneg f32:$rs2))]>;
def FABSS : F3_3u<2, 0b110100, 0b000001001,
                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
                 "fabss $rs2, $rd",
                 [(set f32:$rd, (fabs f32:$rs2))]>;


// Floating-point Square Root Instructions, p.145
def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fsqrts $rs2, $rd",
                  [(set f32:$rd, (fsqrt f32:$rs2))]>;
def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
                  (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
                  "fsqrtd $rs2, $rd",
                  [(set f64:$rd, (fsqrt f64:$rs2))]>;
def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
                  (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
                  "fsqrtq $rs2, $rd",
                  [(set f128:$rd, (fsqrt f128:$rs2))]>,
                  Requires<[HasHardQuad]>;



// Floating-point Add and Subtract Instructions, p. 146
def FADDS  : F3_3<2, 0b110100, 0b001000001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                  "fadds $rs1, $rs2, $rd",
                  [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
def FADDD  : F3_3<2, 0b110100, 0b001000010,
                  (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                  "faddd $rs1, $rs2, $rd",
                  [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
def FADDQ  : F3_3<2, 0b110100, 0b001000011,
                  (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                  "faddq $rs1, $rs2, $rd",
                  [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
                  Requires<[HasHardQuad]>;

def FSUBS  : F3_3<2, 0b110100, 0b001000101,
                  (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                  "fsubs $rs1, $rs2, $rd",
                  [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
def FSUBD  : F3_3<2, 0b110100, 0b001000110,
                  (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                  "fsubd $rs1, $rs2, $rd",
                  [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
def FSUBQ  : F3_3<2, 0b110100, 0b001000111,
                  (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                  "fsubq $rs1, $rs2, $rd",
                  [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
                  Requires<[HasHardQuad]>;


// Floating-point Multiply and Divide Instructions, p. 147
def FMULS  : F3_3<2, 0b110100, 0b001001001,
                  (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                  "fmuls $rs1, $rs2, $rd",
                  [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
def FMULD  : F3_3<2, 0b110100, 0b001001010,
                  (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                  "fmuld $rs1, $rs2, $rd",
                  [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
def FMULQ  : F3_3<2, 0b110100, 0b001001011,
                  (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                  "fmulq $rs1, $rs2, $rd",
                  [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
                  Requires<[HasHardQuad]>;

def FSMULD : F3_3<2, 0b110100, 0b001101001,
                  (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                  "fsmuld $rs1, $rs2, $rd",
                  [(set f64:$rd, (fmul (fextend f32:$rs1),
                                        (fextend f32:$rs2)))]>;
def FDMULQ : F3_3<2, 0b110100, 0b001101110,
                  (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                  "fdmulq $rs1, $rs2, $rd",
                  [(set f128:$rd, (fmul (fextend f64:$rs1),
                                         (fextend f64:$rs2)))]>,
                  Requires<[HasHardQuad]>;

def FDIVS  : F3_3<2, 0b110100, 0b001001101,
                 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                 "fdivs $rs1, $rs2, $rd",
                 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
def FDIVD  : F3_3<2, 0b110100, 0b001001110,
                 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                 "fdivd $rs1, $rs2, $rd",
                 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
                 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                 "fdivq $rs1, $rs2, $rd",
                 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
                 Requires<[HasHardQuad]>;

// Floating-point Compare Instructions, p. 148
// Note: the 2nd template arg is different for these guys.
// Note 2: the result of a FCMP is not available until the 2nd cycle
// after the instr is retired, but there is no interlock in Sparc V8.
// This behavior is modeled with a forced noop after the instruction in
// DelaySlotFiller.

let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
  def FCMPS  : F3_3c<2, 0b110101, 0b001010001,
                   (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fcmps $rs1, $rs2",
                   [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
  def FCMPD  : F3_3c<2, 0b110101, 0b001010010,
                   (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                   "fcmpd $rs1, $rs2",
                   [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
  def FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
                   (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                   "fcmpq $rs1, $rs2",
                   [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
                   Requires<[HasHardQuad]>;
}

//===----------------------------------------------------------------------===//
// Instructions for Thread Local Storage(TLS).
//===----------------------------------------------------------------------===//
let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
def TLS_ADDrr : F3_1<2, 0b000000,
                    (outs IntRegs:$rd),
                    (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
                    "add $rs1, $rs2, $rd, $sym",
                    [(set i32:$rd,
                        (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;

let mayLoad = 1 in
  def TLS_LDrr : F3_1<3, 0b000000,
                      (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
                      "ld [$addr], $dst, $sym",
                      [(set i32:$dst,
                          (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;

let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
  def TLS_CALL : InstSP<(outs),
                        (ins calltarget:$disp, TLSSym:$sym, variable_ops),
                        "call $disp, $sym",
                        [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
  bits<30> disp;
  let op = 1;
  let Inst{29-0} = disp;
}
}

//===----------------------------------------------------------------------===//
// V9 Instructions
//===----------------------------------------------------------------------===//

// V9 Conditional Moves.
let Predicates = [HasV9], Constraints = "$f = $rd" in {
  // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
  let Uses = [ICC], intcc = 1, cc = 0b00 in {
    def MOVICCrr
      : F4_1<0b101100, (outs IntRegs:$rd),
             (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
             "mov$cond %icc, $rs2, $rd",
             [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;

    def MOVICCri
      : F4_2<0b101100, (outs IntRegs:$rd),
             (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
             "mov$cond %icc, $simm11, $rd",
             [(set i32:$rd,
                    (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
  }

  let Uses = [FCC0], intcc = 0, cc = 0b00 in {
    def MOVFCCrr
      : F4_1<0b101100, (outs IntRegs:$rd),
             (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
             "mov$cond %fcc0, $rs2, $rd",
             [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
    def MOVFCCri
      : F4_2<0b101100, (outs IntRegs:$rd),
             (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
             "mov$cond %fcc0, $simm11, $rd",
             [(set i32:$rd,
                    (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
  }

  let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
    def FMOVS_ICC
      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
             (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
             "fmovs$cond %icc, $rs2, $rd",
             [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
    def FMOVD_ICC
      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
               (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
               "fmovd$cond %icc, $rs2, $rd",
               [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
    def FMOVQ_ICC
      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
               (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
               "fmovq$cond %icc, $rs2, $rd",
               [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
               Requires<[HasHardQuad]>;
  }

  let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
    def FMOVS_FCC
      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
             (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
             "fmovs$cond %fcc0, $rs2, $rd",
             [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
    def FMOVD_FCC
      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
             (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
             "fmovd$cond %fcc0, $rs2, $rd",
             [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
    def FMOVQ_FCC
      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
             (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
             "fmovq$cond %fcc0, $rs2, $rd",
             [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
             Requires<[HasHardQuad]>;
  }

}

// Floating-Point Move Instructions, p. 164 of the V9 manual.
let Predicates = [HasV9] in {
  def FMOVD : F3_3u<2, 0b110100, 0b000000010,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
                   "fmovd $rs2, $rd", []>;
  def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
                   "fmovq $rs2, $rd", []>,
                   Requires<[HasHardQuad]>;
  def FNEGD : F3_3u<2, 0b110100, 0b000000110,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
                   "fnegd $rs2, $rd",
                   [(set f64:$rd, (fneg f64:$rs2))]>;
  def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
                   "fnegq $rs2, $rd",
                   [(set f128:$rd, (fneg f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
  def FABSD : F3_3u<2, 0b110100, 0b000001010,
                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
                   "fabsd $rs2, $rd",
                   [(set f64:$rd, (fabs f64:$rs2))]>;
  def FABSQ : F3_3u<2, 0b110100, 0b000001011,
                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
                   "fabsq $rs2, $rd",
                   [(set f128:$rd, (fabs f128:$rs2))]>,
                   Requires<[HasHardQuad]>;
}

// Floating-point compare instruction with %fcc0-%fcc3.
def V9FCMPS  : F3_3c<2, 0b110101, 0b001010001,
               (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
               "fcmps $rd, $rs1, $rs2", []>;
def V9FCMPD  : F3_3c<2, 0b110101, 0b001010010,
                (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                "fcmpd $rd, $rs1, $rs2", []>;
def V9FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
                (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                "fcmpq $rd, $rs1, $rs2", []>,
                 Requires<[HasHardQuad]>;

let hasSideEffects = 1 in {
  def V9FCMPES  : F3_3c<2, 0b110101, 0b001010101,
                   (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                   "fcmpes $rd, $rs1, $rs2", []>;
  def V9FCMPED  : F3_3c<2, 0b110101, 0b001010110,
                   (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                   "fcmped $rd, $rs1, $rs2", []>;
  def V9FCMPEQ  : F3_3c<2, 0b110101, 0b001010111,
                   (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                   "fcmpeq $rd, $rs1, $rs2", []>,
                   Requires<[HasHardQuad]>;
}

// Floating point conditional move instrucitons with %fcc0-%fcc3.
let Predicates = [HasV9] in {
  let Constraints = "$f = $rd", intcc = 0 in {
    def V9MOVFCCrr
      : F4_1<0b101100, (outs IntRegs:$rd),
             (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
             "mov$cond $cc, $rs2, $rd", []>;
    def V9MOVFCCri
      : F4_2<0b101100, (outs IntRegs:$rd),
             (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
             "mov$cond $cc, $simm11, $rd", []>;
    def V9FMOVS_FCC
      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
             (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
             "fmovs$cond $opf_cc, $rs2, $rd", []>;
    def V9FMOVD_FCC
      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
             (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
             "fmovd$cond $opf_cc, $rs2, $rd", []>;
    def V9FMOVQ_FCC
      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
             (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
             "fmovq$cond $opf_cc, $rs2, $rd", []>,
             Requires<[HasHardQuad]>;
  } // Constraints = "$f = $rd", ...
} // let Predicates = [hasV9]


// POPCrr - This does a ctpop of a 64-bit register.  As such, we have to clear
// the top 32-bits before using it.  To do this clearing, we use a SRLri X,0.
let rs1 = 0 in
  def POPCrr : F3_1<2, 0b101110,
                    (outs IntRegs:$dst), (ins IntRegs:$src),
                    "popc $src, $dst", []>, Requires<[HasV9]>;
def : Pat<(ctpop i32:$src),
          (POPCrr (SRLri $src, 0))>;

let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
                    "membar $simm13", []>;

// TODO: Should add a CASArr variant. In fact, the CAS instruction,
// unlike other instructions, only comes in a form which requires an
// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
// default unprivileged ASI for SparcV9.  (Also of note: some modern
// SparcV8 implementations provide CASA as an extension, but require
// the use of SparcV8's default ASI, 0xA ("User Data") instead.)
let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
  def CASrr: F3_1_asi<3, 0b111100,
                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                     IntRegs:$swap),
                 "cas [$rs1], $rs2, $rd",
                 [(set i32:$rd,
                     (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;

let Defs = [ICC] in {
defm TADDCC   : F3_12np<"taddcc",   0b100000>;
defm TSUBCC   : F3_12np<"tsubcc",   0b100001>;

let hasSideEffects = 1 in {
  defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
  defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
}
}

//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//

// Small immediates.
def : Pat<(i32 simm13:$val),
          (ORri (i32 G0), imm:$val)>;
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
          (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;


// Global addresses, constant pool entries
let Predicates = [Is32Bit] in {

def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;

// GlobalTLS addresses
def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
          (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
          (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;

// Blockaddress
def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;

// Add reg, lo.  This is used when taking the addr of a global/constpool entry.
def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)),  (ADDri $r, tconstpool:$in)>;
def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
                        (ADDri $r, tblockaddress:$in)>;
}

// Calls:
def : Pat<(call tglobaladdr:$dst),
          (CALL tglobaladdr:$dst)>;
def : Pat<(call texternalsym:$dst),
          (CALL texternalsym:$dst)>;

// Map integer extload's to zextloads.
def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;

// zextload bool -> zextload byte
def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;

// store 0, addr -> store %g0, addr
def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;

// store bar for all atomic_fence in V8.
let Predicates = [HasNoV9] in
  def : Pat<(atomic_fence imm, imm), (STBAR)>;

// atomic_load_32 addr -> load addr
def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;

// atomic_store_32 val, addr -> store val, addr
def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;


include "SparcInstr64Bit.td"
include "SparcInstrVIS.td"
include "SparcInstrAliases.td"