llvm.org GIT mirror llvm / master test / CodeGen / X86 / lea-opt.ll
master

Tree @master (Download .tar.gz)

lea-opt.ll @masterraw · history · blame

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLED
; RUN: llc --disable-x86-lea-opt < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLED

%struct.anon1 = type { i32, i32, i32 }
%struct.anon2 = type { i32, [32 x i32], i32 }

@arr1 = external global [65 x %struct.anon1], align 16
@arr2 = external global [65 x %struct.anon2], align 16

define void @test1(i64 %x) nounwind {
; ENABLED-LABEL: test1:
; ENABLED:       # %bb.0: # %entry
; ENABLED-NEXT:    shlq $2, %rdi
; ENABLED-NEXT:    movl arr1(%rdi,%rdi,2), %ecx
; ENABLED-NEXT:    leaq arr1+4(%rdi,%rdi,2), %rax
; ENABLED-NEXT:    subl arr1+4(%rdi,%rdi,2), %ecx
; ENABLED-NEXT:    addl arr1+8(%rdi,%rdi,2), %ecx
; ENABLED-NEXT:    cmpl $2, %ecx
; ENABLED-NEXT:    je .LBB0_3
; ENABLED-NEXT:  # %bb.1: # %entry
; ENABLED-NEXT:    cmpl $1, %ecx
; ENABLED-NEXT:    jne .LBB0_4
; ENABLED-NEXT:  # %bb.2: # %sw.bb.1
; ENABLED-NEXT:    movl $111, (%rax)
; ENABLED-NEXT:    movl $222, 4(%rax)
; ENABLED-NEXT:    retq
; ENABLED-NEXT:  .LBB0_3: # %sw.bb.2
; ENABLED-NEXT:    movl $333, (%rax) # imm = 0x14D
; ENABLED-NEXT:    movl $444, 4(%rax) # imm = 0x1BC
; ENABLED-NEXT:  .LBB0_4: # %sw.epilog
; ENABLED-NEXT:    retq
;
; DISABLED-LABEL: test1:
; DISABLED:       # %bb.0: # %entry
; DISABLED-NEXT:    shlq $2, %rdi
; DISABLED-NEXT:    movl arr1(%rdi,%rdi,2), %edx
; DISABLED-NEXT:    leaq arr1+4(%rdi,%rdi,2), %rax
; DISABLED-NEXT:    subl arr1+4(%rdi,%rdi,2), %edx
; DISABLED-NEXT:    leaq arr1+8(%rdi,%rdi,2), %rcx
; DISABLED-NEXT:    addl arr1+8(%rdi,%rdi,2), %edx
; DISABLED-NEXT:    cmpl $2, %edx
; DISABLED-NEXT:    je .LBB0_3
; DISABLED-NEXT:  # %bb.1: # %entry
; DISABLED-NEXT:    cmpl $1, %edx
; DISABLED-NEXT:    jne .LBB0_4
; DISABLED-NEXT:  # %bb.2: # %sw.bb.1
; DISABLED-NEXT:    movl $111, (%rax)
; DISABLED-NEXT:    movl $222, (%rcx)
; DISABLED-NEXT:    retq
; DISABLED-NEXT:  .LBB0_3: # %sw.bb.2
; DISABLED-NEXT:    movl $333, (%rax) # imm = 0x14D
; DISABLED-NEXT:    movl $444, (%rcx) # imm = 0x1BC
; DISABLED-NEXT:  .LBB0_4: # %sw.epilog
; DISABLED-NEXT:    retq
entry:
  %a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
  %tmp = load i32, i32* %a, align 4
  %b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
  %tmp1 = load i32, i32* %b, align 4
  %sub = sub i32 %tmp, %tmp1
  %c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
  %tmp2 = load i32, i32* %c, align 4
  %add = add nsw i32 %sub, %tmp2
  switch i32 %add, label %sw.epilog [
    i32 1, label %sw.bb.1
    i32 2, label %sw.bb.2
  ]

sw.bb.1:                                          ; preds = %entry
  store i32 111, i32* %b, align 4
  store i32 222, i32* %c, align 4
  br label %sw.epilog

sw.bb.2:                                          ; preds = %entry
  store i32 333, i32* %b, align 4
  store i32 444, i32* %c, align 4
  br label %sw.epilog

sw.epilog:                                        ; preds = %sw.bb.2, %sw.bb.1, %entry
  ret void
}

define void @test2(i64 %x) nounwind optsize {
; ENABLED-LABEL: test2:
; ENABLED:       # %bb.0: # %entry
; ENABLED-NEXT:    shlq $2, %rdi
; ENABLED-NEXT:    leaq arr1+4(%rdi,%rdi,2), %rax
; ENABLED-NEXT:    movl -4(%rax), %ecx
; ENABLED-NEXT:    subl (%rax), %ecx
; ENABLED-NEXT:    addl 4(%rax), %ecx
; ENABLED-NEXT:    cmpl $2, %ecx
; ENABLED-NEXT:    je .LBB1_3
; ENABLED-NEXT:  # %bb.1: # %entry
; ENABLED-NEXT:    cmpl $1, %ecx
; ENABLED-NEXT:    jne .LBB1_4
; ENABLED-NEXT:  # %bb.2: # %sw.bb.1
; ENABLED-NEXT:    movl $111, (%rax)
; ENABLED-NEXT:    movl $222, 4(%rax)
; ENABLED-NEXT:    retq
; ENABLED-NEXT:  .LBB1_3: # %sw.bb.2
; ENABLED-NEXT:    movl $333, (%rax) # imm = 0x14D
; ENABLED-NEXT:    movl $444, 4(%rax) # imm = 0x1BC
; ENABLED-NEXT:  .LBB1_4: # %sw.epilog
; ENABLED-NEXT:    retq
;
; DISABLED-LABEL: test2:
; DISABLED:       # %bb.0: # %entry
; DISABLED-NEXT:    shlq $2, %rdi
; DISABLED-NEXT:    movl arr1(%rdi,%rdi,2), %edx
; DISABLED-NEXT:    leaq arr1+4(%rdi,%rdi,2), %rax
; DISABLED-NEXT:    subl arr1+4(%rdi,%rdi,2), %edx
; DISABLED-NEXT:    leaq arr1+8(%rdi,%rdi,2), %rcx
; DISABLED-NEXT:    addl arr1+8(%rdi,%rdi,2), %edx
; DISABLED-NEXT:    cmpl $2, %edx
; DISABLED-NEXT:    je .LBB1_3
; DISABLED-NEXT:  # %bb.1: # %entry
; DISABLED-NEXT:    cmpl $1, %edx
; DISABLED-NEXT:    jne .LBB1_4
; DISABLED-NEXT:  # %bb.2: # %sw.bb.1
; DISABLED-NEXT:    movl $111, (%rax)
; DISABLED-NEXT:    movl $222, (%rcx)
; DISABLED-NEXT:    retq
; DISABLED-NEXT:  .LBB1_3: # %sw.bb.2
; DISABLED-NEXT:    movl $333, (%rax) # imm = 0x14D
; DISABLED-NEXT:    movl $444, (%rcx) # imm = 0x1BC
; DISABLED-NEXT:  .LBB1_4: # %sw.epilog
; DISABLED-NEXT:    retq
entry:
  %a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
  %tmp = load i32, i32* %a, align 4
  %b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
  %tmp1 = load i32, i32* %b, align 4
  %sub = sub i32 %tmp, %tmp1
  %c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
  %tmp2 = load i32, i32* %c, align 4
  %add = add nsw i32 %sub, %tmp2
  switch i32 %add, label %sw.epilog [
    i32 1, label %sw.bb.1
    i32 2, label %sw.bb.2
  ]

sw.bb.1:                                          ; preds = %entry
  store i32 111, i32* %b, align 4
  store i32 222, i32* %c, align 4
  br label %sw.epilog

sw.bb.2:                                          ; preds = %entry
  store i32 333, i32* %b, align 4
  store i32 444, i32* %c, align 4
  br label %sw.epilog

sw.epilog:                                        ; preds = %sw.bb.2, %sw.bb.1, %entry
  ret void
}

; Check that LEA optimization pass takes into account a resultant address
; displacement when choosing a LEA instruction for replacing a redundant
; address recalculation.

define void @test3(i64 %x) nounwind optsize {
; ENABLED-LABEL: test3:
; ENABLED:       # %bb.0: # %entry
; ENABLED-NEXT:    movq %rdi, %rax
; ENABLED-NEXT:    shlq $7, %rax
; ENABLED-NEXT:    leaq arr2+132(%rax,%rdi,8), %rcx
; ENABLED-NEXT:    leaq arr2(%rax,%rdi,8), %rax
; ENABLED-NEXT:    movl (%rcx), %edx
; ENABLED-NEXT:    addl (%rax), %edx
; ENABLED-NEXT:    cmpl $2, %edx
; ENABLED-NEXT:    je .LBB2_3
; ENABLED-NEXT:  # %bb.1: # %entry
; ENABLED-NEXT:    cmpl $1, %edx
; ENABLED-NEXT:    jne .LBB2_4
; ENABLED-NEXT:  # %bb.2: # %sw.bb.1
; ENABLED-NEXT:    movl $111, (%rcx)
; ENABLED-NEXT:    movl $222, (%rax)
; ENABLED-NEXT:    retq
; ENABLED-NEXT:  .LBB2_3: # %sw.bb.2
; ENABLED-NEXT:    movl $333, (%rcx) # imm = 0x14D
; ENABLED-NEXT:    movl %eax, (%rax)
; ENABLED-NEXT:  .LBB2_4: # %sw.epilog
; ENABLED-NEXT:    retq
;
; DISABLED-LABEL: test3:
; DISABLED:       # %bb.0: # %entry
; DISABLED-NEXT:    movq %rdi, %rsi
; DISABLED-NEXT:    shlq $7, %rsi
; DISABLED-NEXT:    leaq arr2+132(%rsi,%rdi,8), %rcx
; DISABLED-NEXT:    leaq arr2(%rsi,%rdi,8), %rax
; DISABLED-NEXT:    movl arr2+132(%rsi,%rdi,8), %edx
; DISABLED-NEXT:    addl arr2(%rsi,%rdi,8), %edx
; DISABLED-NEXT:    cmpl $2, %edx
; DISABLED-NEXT:    je .LBB2_3
; DISABLED-NEXT:  # %bb.1: # %entry
; DISABLED-NEXT:    cmpl $1, %edx
; DISABLED-NEXT:    jne .LBB2_4
; DISABLED-NEXT:  # %bb.2: # %sw.bb.1
; DISABLED-NEXT:    movl $111, (%rcx)
; DISABLED-NEXT:    movl $222, (%rax)
; DISABLED-NEXT:    retq
; DISABLED-NEXT:  .LBB2_3: # %sw.bb.2
; DISABLED-NEXT:    movl $333, (%rcx) # imm = 0x14D
; DISABLED-NEXT:    movl %eax, (%rax)
; DISABLED-NEXT:  .LBB2_4: # %sw.epilog
; DISABLED-NEXT:    retq
entry:
  %a = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 2
  %tmp = load i32, i32* %a, align 4
  %b = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 0
  %tmp1 = load i32, i32* %b, align 4
  %add = add nsw i32 %tmp, %tmp1
  switch i32 %add, label %sw.epilog [
    i32 1, label %sw.bb.1
    i32 2, label %sw.bb.2
  ]

sw.bb.1:                                          ; preds = %entry
  store i32 111, i32* %a, align 4
  store i32 222, i32* %b, align 4
  br label %sw.epilog

sw.bb.2:                                          ; preds = %entry
  store i32 333, i32* %a, align 4
  ; Make sure the REG3's definition LEA won't be removed as redundant.
  %cvt = ptrtoint i32* %b to i32
  store i32 %cvt, i32* %b, align 4
  br label %sw.epilog

sw.epilog:                                        ; preds = %sw.bb.2, %sw.bb.1, %entry
  ret void

; REG3's definition is closer to movl than REG2's, but the pass still chooses
; REG2 because it provides the resultant address displacement fitting 1 byte.

}

define void @test4(i64 %x) nounwind minsize {
; ENABLED-LABEL: test4:
; ENABLED:       # %bb.0: # %entry
; ENABLED-NEXT:    imulq $12, %rdi, %rax
; ENABLED-NEXT:    leaq arr1+4(%rax), %rax
; ENABLED-NEXT:    movl -4(%rax), %ecx
; ENABLED-NEXT:    subl (%rax), %ecx
; ENABLED-NEXT:    addl 4(%rax), %ecx
; ENABLED-NEXT:    cmpl $2, %ecx
; ENABLED-NEXT:    je .LBB3_3
; ENABLED-NEXT:  # %bb.1: # %entry
; ENABLED-NEXT:    cmpl $1, %ecx
; ENABLED-NEXT:    jne .LBB3_4
; ENABLED-NEXT:  # %bb.2: # %sw.bb.1
; ENABLED-NEXT:    movl $111, (%rax)
; ENABLED-NEXT:    movl $222, 4(%rax)
; ENABLED-NEXT:    retq
; ENABLED-NEXT:  .LBB3_3: # %sw.bb.2
; ENABLED-NEXT:    movl $333, (%rax) # imm = 0x14D
; ENABLED-NEXT:    movl $444, 4(%rax) # imm = 0x1BC
; ENABLED-NEXT:  .LBB3_4: # %sw.epilog
; ENABLED-NEXT:    retq
;
; DISABLED-LABEL: test4:
; DISABLED:       # %bb.0: # %entry
; DISABLED-NEXT:    imulq $12, %rdi, %rsi
; DISABLED-NEXT:    movl arr1(%rsi), %edx
; DISABLED-NEXT:    leaq arr1+4(%rsi), %rax
; DISABLED-NEXT:    subl arr1+4(%rsi), %edx
; DISABLED-NEXT:    leaq arr1+8(%rsi), %rcx
; DISABLED-NEXT:    addl arr1+8(%rsi), %edx
; DISABLED-NEXT:    cmpl $2, %edx
; DISABLED-NEXT:    je .LBB3_3
; DISABLED-NEXT:  # %bb.1: # %entry
; DISABLED-NEXT:    cmpl $1, %edx
; DISABLED-NEXT:    jne .LBB3_4
; DISABLED-NEXT:  # %bb.2: # %sw.bb.1
; DISABLED-NEXT:    movl $111, (%rax)
; DISABLED-NEXT:    movl $222, (%rcx)
; DISABLED-NEXT:    retq
; DISABLED-NEXT:  .LBB3_3: # %sw.bb.2
; DISABLED-NEXT:    movl $333, (%rax) # imm = 0x14D
; DISABLED-NEXT:    movl $444, (%rcx) # imm = 0x1BC
; DISABLED-NEXT:  .LBB3_4: # %sw.epilog
; DISABLED-NEXT:    retq
entry:
  %a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
  %tmp = load i32, i32* %a, align 4
  %b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
  %tmp1 = load i32, i32* %b, align 4
  %sub = sub i32 %tmp, %tmp1
  %c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
  %tmp2 = load i32, i32* %c, align 4
  %add = add nsw i32 %sub, %tmp2
  switch i32 %add, label %sw.epilog [
    i32 1, label %sw.bb.1
    i32 2, label %sw.bb.2
  ]

sw.bb.1:                                          ; preds = %entry
  store i32 111, i32* %b, align 4
  store i32 222, i32* %c, align 4
  br label %sw.epilog

sw.bb.2:                                          ; preds = %entry
  store i32 333, i32* %b, align 4
  store i32 444, i32* %c, align 4
  br label %sw.epilog

sw.epilog:                                        ; preds = %sw.bb.2, %sw.bb.1, %entry
  ret void
}

define  i32 @test5(i32 %x, i32 %y)  #0 {
; CHECK-LABEL: test5:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    addl %esi, %esi
; CHECK-NEXT:    subl %esi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 %y, -2
  %add = add nsw i32 %mul, %x
  ret i32 %add
}

define  i32 @test6(i32 %x, i32 %y)  #0 {
; CHECK-LABEL: test6:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    leal (%rsi,%rsi,2), %ecx
; CHECK-NEXT:    subl %ecx, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 %y, -3
  %add = add nsw i32 %mul, %x
  ret i32 %add
}

define  i32 @test7(i32 %x, i32 %y)  #0 {
; CHECK-LABEL: test7:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    shll $2, %esi
; CHECK-NEXT:    subl %esi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 %y, -4
  %add = add nsw i32 %mul, %x
  ret i32 %add
}

define  i32 @test8(i32 %x, i32 %y)  #0 {
; CHECK-LABEL: test8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
; CHECK-NEXT:    leal (,%rsi,4), %eax
; CHECK-NEXT:    subl %edi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = shl nsw i32 %y, 2
  %sub = sub nsw i32 %mul, %x
  ret i32 %sub
}


define  i32 @test9(i32 %x, i32 %y) #0 {
; CHECK-LABEL: test9:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    addl %esi, %esi
; CHECK-NEXT:    subl %esi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 -2, %y
  %add = add nsw i32 %x, %mul
  ret i32 %add
}

define  i32 @test10(i32 %x, i32 %y) #0 {
; CHECK-LABEL: test10:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    leal (%rsi,%rsi,2), %ecx
; CHECK-NEXT:    subl %ecx, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 -3, %y
  %add = add nsw i32 %x, %mul
  ret i32 %add
}

define  i32 @test11(i32 %x, i32 %y) #0 {
; CHECK-LABEL: test11:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    shll $2, %esi
; CHECK-NEXT:    subl %esi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 -4, %y
  %add = add nsw i32 %x, %mul
  ret i32 %add
}

define  i32 @test12(i32 %x, i32 %y) #0 {
; CHECK-LABEL: test12:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
; CHECK-NEXT:    leal (,%rsi,4), %eax
; CHECK-NEXT:    subl %edi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 4, %y
  %sub = sub nsw i32 %mul, %x
  ret i32 %sub
}

define  i64 @test13(i64 %x, i64 %y) #0 {
; CHECK-LABEL: test13:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movq %rdi, %rax
; CHECK-NEXT:    shlq $2, %rsi
; CHECK-NEXT:    subq %rsi, %rax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i64 -4, %y
  %add = add nsw i64 %x, %mul
  ret i64 %add
}

define  i32 @test14(i32 %x, i32 %y) #0 {
; CHECK-LABEL: test14:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
; CHECK-NEXT:    leal (,%rsi,4), %eax
; CHECK-NEXT:    subl %edi, %eax
; CHECK-NEXT:    retq
entry:
  %mul = mul nsw i32 4, %y
  %sub = sub nsw i32 %mul, %x
  ret i32 %sub
}

define  zeroext i16 @test15(i16 zeroext %x, i16 zeroext %y) #0 {
; CHECK-LABEL: test15:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    shll $3, %esi
; CHECK-NEXT:    subl %esi, %eax
; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
; CHECK-NEXT:    retq
entry:
  %conv = zext i16 %x to i32
  %conv1 = zext i16 %y to i32
  %mul = mul nsw i32 -8, %conv1
  %add = add nsw i32 %conv, %mul
  %conv2 = trunc i32 %add to i16
  ret i16 %conv2
}

attributes #0 = { norecurse nounwind optsize readnone uwtable}