llvm.org GIT mirror llvm / master test / CodeGen / PowerPC / pre-inc-disable.ll
master

Tree @master (Download .tar.gz)

pre-inc-disable.ll @masterraw · history · blame

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
; RUN:     -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:     < %s | FileCheck %s

; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
; RUN:     -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
; RUN:     < %s | FileCheck %s --check-prefix=P9BE

; Function Attrs: norecurse nounwind readonly
define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lfd f0, 0(r5)
; CHECK-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
; CHECK-NEXT:    addi r5, r5, .LCPI0_0@toc@l
; CHECK-NEXT:    lxvx v2, 0, r5
; CHECK-NEXT:    addis r5, r2, .LCPI0_1@toc@ha
; CHECK-NEXT:    addi r5, r5, .LCPI0_1@toc@l
; CHECK-NEXT:    lxvx v4, 0, r5
; CHECK-NEXT:    xxpermdi v5, f0, f0, 2
; CHECK-NEXT:    xxlxor v3, v3, v3
; CHECK-NEXT:    li r5, 4
; CHECK-NEXT:    vperm v0, v3, v5, v2
; CHECK-NEXT:    mtctr r5
; CHECK-NEXT:    li r5, 0
; CHECK-NEXT:    vperm v1, v5, v3, v4
; CHECK-NEXT:    li r6, 0
; CHECK-NEXT:    xvnegsp v5, v0
; CHECK-NEXT:    xvnegsp v0, v1
; CHECK-NEXT:    .p2align 4
; CHECK-NEXT:  .LBB0_1: # %for.cond1.preheader
; CHECK-NEXT:    #
; CHECK-NEXT:    lfd f0, 0(r3)
; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
; CHECK-NEXT:    vperm v6, v1, v3, v4
; CHECK-NEXT:    vperm v1, v3, v1, v2
; CHECK-NEXT:    xvnegsp v1, v1
; CHECK-NEXT:    xvnegsp v6, v6
; CHECK-NEXT:    vabsduw v1, v1, v5
; CHECK-NEXT:    vabsduw v6, v6, v0
; CHECK-NEXT:    vadduwm v1, v6, v1
; CHECK-NEXT:    xxswapd v6, v1
; CHECK-NEXT:    vadduwm v1, v1, v6
; CHECK-NEXT:    xxspltw v6, v1, 2
; CHECK-NEXT:    vadduwm v1, v1, v6
; CHECK-NEXT:    vextuwrx r7, r5, v1
; CHECK-NEXT:    lfdx f0, r3, r4
; CHECK-NEXT:    add r6, r7, r6
; CHECK-NEXT:    add r7, r3, r4
; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
; CHECK-NEXT:    add r3, r7, r4
; CHECK-NEXT:    vperm v6, v3, v1, v2
; CHECK-NEXT:    vperm v1, v1, v3, v4
; CHECK-NEXT:    xvnegsp v6, v6
; CHECK-NEXT:    xvnegsp v1, v1
; CHECK-NEXT:    vabsduw v6, v6, v5
; CHECK-NEXT:    vabsduw v1, v1, v0
; CHECK-NEXT:    vadduwm v1, v1, v6
; CHECK-NEXT:    xxswapd v6, v1
; CHECK-NEXT:    vadduwm v1, v1, v6
; CHECK-NEXT:    xxspltw v6, v1, 2
; CHECK-NEXT:    vadduwm v1, v1, v6
; CHECK-NEXT:    vextuwrx r8, r5, v1
; CHECK-NEXT:    add r6, r8, r6
; CHECK-NEXT:    bdnz .LBB0_1
; CHECK-NEXT:  # %bb.2: # %for.cond.cleanup
; CHECK-NEXT:    extsw r3, r6
; CHECK-NEXT:    blr
;
; P9BE-LABEL: test_pre_inc_disable_1:
; P9BE:       # %bb.0: # %entry
; P9BE-NEXT:    lfd f0, 0(r5)
; P9BE-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
; P9BE-NEXT:    addi r5, r5, .LCPI0_0@toc@l
; P9BE-NEXT:    lxvx v2, 0, r5
; P9BE-NEXT:    addis r5, r2, .LCPI0_1@toc@ha
; P9BE-NEXT:    addi r5, r5, .LCPI0_1@toc@l
; P9BE-NEXT:    lxvx v4, 0, r5
; P9BE-NEXT:    li r5, 4
; P9BE-NEXT:    xxlor v5, vs0, vs0
; P9BE-NEXT:    xxlxor v3, v3, v3
; P9BE-NEXT:    vperm v0, v3, v5, v2
; P9BE-NEXT:    mtctr r5
; P9BE-NEXT:    li r5, 0
; P9BE-NEXT:    vperm v1, v3, v5, v4
; P9BE-NEXT:    li r6, 0
; P9BE-NEXT:    xvnegsp v5, v0
; P9BE-NEXT:    xvnegsp v0, v1
; P9BE-NEXT:    .p2align 4
; P9BE-NEXT:  .LBB0_1: # %for.cond1.preheader
; P9BE-NEXT:    #
; P9BE-NEXT:    lfd f0, 0(r3)
; P9BE-NEXT:    xxlor v1, vs0, vs0
; P9BE-NEXT:    vperm v6, v3, v1, v4
; P9BE-NEXT:    vperm v1, v3, v1, v2
; P9BE-NEXT:    xvnegsp v1, v1
; P9BE-NEXT:    xvnegsp v6, v6
; P9BE-NEXT:    vabsduw v1, v1, v5
; P9BE-NEXT:    vabsduw v6, v6, v0
; P9BE-NEXT:    vadduwm v1, v6, v1
; P9BE-NEXT:    xxswapd v6, v1
; P9BE-NEXT:    vadduwm v1, v1, v6
; P9BE-NEXT:    xxspltw v6, v1, 1
; P9BE-NEXT:    vadduwm v1, v1, v6
; P9BE-NEXT:    vextuwlx r7, r5, v1
; P9BE-NEXT:    lfdx f0, r3, r4
; P9BE-NEXT:    add r6, r7, r6
; P9BE-NEXT:    add r7, r3, r4
; P9BE-NEXT:    xxlor v1, vs0, vs0
; P9BE-NEXT:    add r3, r7, r4
; P9BE-NEXT:    vperm v6, v3, v1, v2
; P9BE-NEXT:    vperm v1, v3, v1, v4
; P9BE-NEXT:    xvnegsp v6, v6
; P9BE-NEXT:    xvnegsp v1, v1
; P9BE-NEXT:    vabsduw v6, v6, v5
; P9BE-NEXT:    vabsduw v1, v1, v0
; P9BE-NEXT:    vadduwm v1, v1, v6
; P9BE-NEXT:    xxswapd v6, v1
; P9BE-NEXT:    vadduwm v1, v1, v6
; P9BE-NEXT:    xxspltw v6, v1, 1
; P9BE-NEXT:    vadduwm v1, v1, v6
; P9BE-NEXT:    vextuwlx r8, r5, v1
; P9BE-NEXT:    add r6, r8, r6
; P9BE-NEXT:    bdnz .LBB0_1
; P9BE-NEXT:  # %bb.2: # %for.cond.cleanup
; P9BE-NEXT:    extsw r3, r6
; P9BE-NEXT:    blr
entry:
  %idx.ext = sext i32 %i_stride_pix1 to i64
  %0 = bitcast i8* %pix2 to <8 x i8>*
  %1 = load <8 x i8>, <8 x i8>* %0, align 1
  %2 = zext <8 x i8> %1 to <8 x i32>
  br label %for.cond1.preheader

for.cond1.preheader:                              ; preds = %for.cond1.preheader, %entry
  %y.024 = phi i32 [ 0, %entry ], [ %inc9.1, %for.cond1.preheader ]
  %i_sum.023 = phi i32 [ 0, %entry ], [ %op.extra.1, %for.cond1.preheader ]
  %pix1.addr.022 = phi i8* [ %pix1, %entry ], [ %add.ptr.1, %for.cond1.preheader ]
  %3 = bitcast i8* %pix1.addr.022 to <8 x i8>*
  %4 = load <8 x i8>, <8 x i8>* %3, align 1
  %5 = zext <8 x i8> %4 to <8 x i32>
  %6 = sub nsw <8 x i32> %5, %2
  %7 = icmp slt <8 x i32> %6, zeroinitializer
  %8 = sub nsw <8 x i32> zeroinitializer, %6
  %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
  %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
  %rdx.shuf32 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx33 = add nsw <8 x i32> %bin.rdx, %rdx.shuf32
  %rdx.shuf34 = shufflevector <8 x i32> %bin.rdx33, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx35 = add nsw <8 x i32> %bin.rdx33, %rdx.shuf34
  %10 = extractelement <8 x i32> %bin.rdx35, i32 0
  %op.extra = add nsw i32 %10, %i_sum.023
  %add.ptr = getelementptr inbounds i8, i8* %pix1.addr.022, i64 %idx.ext
  %11 = bitcast i8* %add.ptr to <8 x i8>*
  %12 = load <8 x i8>, <8 x i8>* %11, align 1
  %13 = zext <8 x i8> %12 to <8 x i32>
  %14 = sub nsw <8 x i32> %13, %2
  %15 = icmp slt <8 x i32> %14, zeroinitializer
  %16 = sub nsw <8 x i32> zeroinitializer, %14
  %17 = select <8 x i1> %15, <8 x i32> %16, <8 x i32> %14
  %rdx.shuf.1 = shufflevector <8 x i32> %17, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx.1 = add nsw <8 x i32> %17, %rdx.shuf.1
  %rdx.shuf32.1 = shufflevector <8 x i32> %bin.rdx.1, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx33.1 = add nsw <8 x i32> %bin.rdx.1, %rdx.shuf32.1
  %rdx.shuf34.1 = shufflevector <8 x i32> %bin.rdx33.1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx35.1 = add nsw <8 x i32> %bin.rdx33.1, %rdx.shuf34.1
  %18 = extractelement <8 x i32> %bin.rdx35.1, i32 0
  %op.extra.1 = add nsw i32 %18, %op.extra
  %add.ptr.1 = getelementptr inbounds i8, i8* %add.ptr, i64 %idx.ext
  %inc9.1 = add nuw nsw i32 %y.024, 2
  %exitcond.1 = icmp eq i32 %inc9.1, 8
  br i1 %exitcond.1, label %for.cond.cleanup, label %for.cond1.preheader

for.cond.cleanup:                                 ; preds = %for.cond1.preheader
  ret i32 %op.extra.1
}

; Function Attrs: norecurse nounwind readonly
define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lfd f0, 0(r3)
; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
; CHECK-NEXT:    lxvx v4, 0, r3
; CHECK-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
; CHECK-NEXT:    lfd f0, 0(r4)
; CHECK-NEXT:    addi r3, r3, .LCPI1_1@toc@l
; CHECK-NEXT:    xxlxor v3, v3, v3
; CHECK-NEXT:    lxvx v0, 0, r3
; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
; CHECK-NEXT:    vperm v5, v2, v3, v4
; CHECK-NEXT:    vperm v2, v3, v2, v0
; CHECK-NEXT:    vperm v0, v3, v1, v0
; CHECK-NEXT:    vperm v3, v1, v3, v4
; CHECK-NEXT:    vabsduw v2, v2, v0
; CHECK-NEXT:    vabsduw v3, v5, v3
; CHECK-NEXT:    vadduwm v2, v3, v2
; CHECK-NEXT:    xxswapd v3, v2
; CHECK-NEXT:    li r3, 0
; CHECK-NEXT:    vadduwm v2, v2, v3
; CHECK-NEXT:    xxspltw v3, v2, 2
; CHECK-NEXT:    vadduwm v2, v2, v3
; CHECK-NEXT:    vextuwrx r3, r3, v2
; CHECK-NEXT:    extsw r3, r3
; CHECK-NEXT:    blr
;
; P9BE-LABEL: test_pre_inc_disable_2:
; P9BE:       # %bb.0: # %entry
; P9BE-NEXT:    lfd f0, 0(r3)
; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
; P9BE-NEXT:    lxvx v4, 0, r3
; P9BE-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
; P9BE-NEXT:    addi r3, r3, .LCPI1_1@toc@l
; P9BE-NEXT:    xxlor v2, vs0, vs0
; P9BE-NEXT:    lfd f0, 0(r4)
; P9BE-NEXT:    lxvx v0, 0, r3
; P9BE-NEXT:    xxlxor v3, v3, v3
; P9BE-NEXT:    xxlor v1, vs0, vs0
; P9BE-NEXT:    vperm v5, v3, v2, v4
; P9BE-NEXT:    vperm v2, v3, v2, v0
; P9BE-NEXT:    vperm v0, v3, v1, v0
; P9BE-NEXT:    vperm v3, v3, v1, v4
; P9BE-NEXT:    vabsduw v2, v2, v0
; P9BE-NEXT:    vabsduw v3, v5, v3
; P9BE-NEXT:    vadduwm v2, v3, v2
; P9BE-NEXT:    xxswapd v3, v2
; P9BE-NEXT:    vadduwm v2, v2, v3
; P9BE-NEXT:    xxspltw v3, v2, 1
; P9BE-NEXT:    vadduwm v2, v2, v3
; P9BE-NEXT:    li r3, 0
; P9BE-NEXT:    vextuwlx r3, r3, v2
; P9BE-NEXT:    extsw r3, r3
; P9BE-NEXT:    blr
entry:
  %0 = bitcast i8* %pix1 to <8 x i8>*
  %1 = load <8 x i8>, <8 x i8>* %0, align 1
  %2 = zext <8 x i8> %1 to <8 x i32>
  %3 = bitcast i8* %pix2 to <8 x i8>*
  %4 = load <8 x i8>, <8 x i8>* %3, align 1
  %5 = zext <8 x i8> %4 to <8 x i32>
  %6 = sub nsw <8 x i32> %2, %5
  %7 = icmp slt <8 x i32> %6, zeroinitializer
  %8 = sub nsw <8 x i32> zeroinitializer, %6
  %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
  %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
  %rdx.shuf12 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx13 = add nsw <8 x i32> %bin.rdx, %rdx.shuf12
  %rdx.shuf14 = shufflevector <8 x i32> %bin.rdx13, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx15 = add nsw <8 x i32> %bin.rdx13, %rdx.shuf14
  %10 = extractelement <8 x i32> %bin.rdx15, i32 0
  ret i32 %10
}


; Generated from C source:
;
;#include <stdint.h>
;#include <stdlib.h>
;int test_pre_inc_disable_1( uint8_t *pix1, int i_stride_pix1, uint8_t *pix2 ) {
;    int i_sum = 0;
;    for( int y = 0; y < 8; y++ ) {
;        for( int x = 0; x < 8; x++) {
;            i_sum += abs( pix1[x] - pix2[x] )
;        }
;        pix1 += i_stride_pix1;
;    }
;    return i_sum;
;}

;int test_pre_inc_disable_2( uint8_t *pix1, uint8_t *pix2 ) {
;  int i_sum = 0;
;  for( int x = 0; x < 8; x++ ) {
;    i_sum += abs( pix1[x] - pix2[x] );
;  }
;
;  return i_sum;
;}

define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
; CHECK-LABEL: test32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    add r5, r3, r4
; CHECK-NEXT:    lfiwzx f0, r3, r4
; CHECK-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI2_0@toc@l
; CHECK-NEXT:    lxvx v4, 0, r3
; CHECK-NEXT:    li r3, 4
; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
; CHECK-NEXT:    lfiwzx f0, r5, r3
; CHECK-NEXT:    xxlxor v3, v3, v3
; CHECK-NEXT:    vperm v2, v2, v3, v4
; CHECK-NEXT:    xxpermdi v5, f0, f0, 2
; CHECK-NEXT:    vperm v3, v5, v3, v4
; CHECK-NEXT:    vspltisw v4, 8
; CHECK-NEXT:    vnegw v3, v3
; CHECK-NEXT:    vadduwm v4, v4, v4
; CHECK-NEXT:    vslw v3, v3, v4
; CHECK-NEXT:    vsubuwm v2, v3, v2
; CHECK-NEXT:    xxswapd vs0, v2
; CHECK-NEXT:    stxvx vs0, 0, r3
; CHECK-NEXT:    blr
;
; P9BE-LABEL: test32:
; P9BE:       # %bb.0: # %entry
; P9BE-NEXT:    add r5, r3, r4
; P9BE-NEXT:    lfiwzx f0, r3, r4
; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
; P9BE-NEXT:    lxvx v4, 0, r3
; P9BE-NEXT:    li r3, 4
; P9BE-NEXT:    xxsldwi v2, f0, f0, 1
; P9BE-NEXT:    lfiwzx f0, r5, r3
; P9BE-NEXT:    xxlxor v3, v3, v3
; P9BE-NEXT:    vperm v2, v3, v2, v4
; P9BE-NEXT:    xxsldwi v5, f0, f0, 1
; P9BE-NEXT:    vperm v3, v3, v5, v4
; P9BE-NEXT:    vspltisw v4, 8
; P9BE-NEXT:    vnegw v3, v3
; P9BE-NEXT:    vadduwm v4, v4, v4
; P9BE-NEXT:    vslw v3, v3, v4
; P9BE-NEXT:    vsubuwm v2, v3, v2
; P9BE-NEXT:    xxswapd vs0, v2
; P9BE-NEXT:    stxvx vs0, 0, r3
; P9BE-NEXT:    blr
entry:
  %idx.ext63 = sext i32 %i_pix2 to i64
  %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
  %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
  %0 = bitcast i8* %add.ptr64 to <4 x i8>*
  %1 = load <4 x i8>, <4 x i8>* %0, align 1
  %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  %2 = zext <4 x i8> %reorder_shuffle117 to <4 x i32>
  %3 = sub nsw <4 x i32> zeroinitializer, %2
  %4 = bitcast i8* %arrayidx5.1 to <4 x i8>*
  %5 = load <4 x i8>, <4 x i8>* %4, align 1
  %reorder_shuffle115 = shufflevector <4 x i8> %5, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  %6 = zext <4 x i8> %reorder_shuffle115 to <4 x i32>
  %7 = sub nsw <4 x i32> zeroinitializer, %6
  %8 = shl nsw <4 x i32> %7, <i32 16, i32 16, i32 16, i32 16>
  %9 = add nsw <4 x i32> %8, %3
  %10 = sub nsw <4 x i32> %9, zeroinitializer
  %11 = shufflevector <4 x i32> undef, <4 x i32> %10, <4 x i32> <i32 2, i32 7, i32 0, i32 5>
  %12 = add nsw <4 x i32> zeroinitializer, %11
  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
  store <4 x i32> %13, <4 x i32>* undef, align 16
  ret void
}

define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
; CHECK-LABEL: test16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sldi r4, r4, 1
; CHECK-NEXT:    lxsihzx v2, r3, r4
; CHECK-NEXT:    vsplth v2, v2, 3
; CHECK-NEXT:    xxlxor v3, v3, v3
; CHECK-NEXT:    vmrglh v2, v3, v2
; CHECK-NEXT:    vsplth v4, v3, 7
; CHECK-NEXT:    add r6, r3, r4
; CHECK-NEXT:    li r3, 16
; CHECK-NEXT:    vmrglw v2, v2, v4
; CHECK-NEXT:    lxsihzx v4, r6, r3
; CHECK-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT:    vsplth v4, v4, 3
; CHECK-NEXT:    vmrglh v3, v3, v4
; CHECK-NEXT:    lxvx v4, 0, r3
; CHECK-NEXT:    li r3, 0
; CHECK-NEXT:    vperm v2, v3, v2, v4
; CHECK-NEXT:    xxspltw v3, v2, 2
; CHECK-NEXT:    vadduwm v2, v2, v3
; CHECK-NEXT:    vextuwrx r3, r3, v2
; CHECK-NEXT:    cmpw cr0, r3, r5
; CHECK-NEXT:    bgelr+ cr0
; CHECK-NEXT:  # %bb.1: # %if.then
;
; P9BE-LABEL: test16:
; P9BE:       # %bb.0: # %entry
; P9BE-NEXT:    sldi r4, r4, 1
; P9BE-NEXT:    add r6, r3, r4
; P9BE-NEXT:    li r7, 16
; P9BE-NEXT:    lxsihzx v2, r6, r7
; P9BE-NEXT:    vsplth v2, v2, 3
; P9BE-NEXT:    lxsihzx v4, r3, r4
; P9BE-NEXT:    li r6, 0
; P9BE-NEXT:    sldi r6, r6, 48
; P9BE-NEXT:    mtvsrd v3, r6
; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
; P9BE-NEXT:    vmrghh v2, v3, v2
; P9BE-NEXT:    vsplth v4, v4, 3
; P9BE-NEXT:    vmrghh v4, v3, v4
; P9BE-NEXT:    vsplth v3, v3, 0
; P9BE-NEXT:    vmrghw v3, v3, v4
; P9BE-NEXT:    lxvx v4, 0, r3
; P9BE-NEXT:    li r3, 0
; P9BE-NEXT:    vperm v2, v3, v2, v4
; P9BE-NEXT:    xxspltw v3, v2, 1
; P9BE-NEXT:    vadduwm v2, v2, v3
; P9BE-NEXT:    vextuwlx r3, r3, v2
; P9BE-NEXT:    cmpw cr0, r3, r5
; P9BE-NEXT:    bgelr+ cr0
; P9BE-NEXT:  # %bb.1: # %if.then
entry:
  %idxprom = sext i32 %delta to i64
  %add14 = add nsw i32 %delta, 8
  %idxprom15 = sext i32 %add14 to i64
  br label %for.body

for.body:                                         ; preds = %entry
  %arrayidx8 = getelementptr inbounds i16, i16* %sums, i64 %idxprom
  %0 = load i16, i16* %arrayidx8, align 2
  %arrayidx16 = getelementptr inbounds i16, i16* %sums, i64 %idxprom15
  %1 = load i16, i16* %arrayidx16, align 2
  %2 = insertelement <4 x i16> undef, i16 %0, i32 2
  %3 = insertelement <4 x i16> %2, i16 %1, i32 3
  %4 = zext <4 x i16> %3 to <4 x i32>
  %5 = sub nsw <4 x i32> zeroinitializer, %4
  %6 = sub nsw <4 x i32> zeroinitializer, %5
  %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
  %bin.rdx = add <4 x i32> %7, zeroinitializer
  %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
  %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
  %8 = extractelement <4 x i32> %bin.rdx55, i32 0
  %op.extra = add nuw i32 %8, 0
  %cmp25 = icmp slt i32 %op.extra, %thresh
  br i1 %cmp25, label %if.then, label %if.end

if.then:                                          ; preds = %for.body
  unreachable

if.end:                                           ; preds = %for.body
  ret void
}

define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
; CHECK-LABEL: test8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxsibzx v2, r3, r4
; CHECK-NEXT:    add r6, r3, r4
; CHECK-NEXT:    li r3, 0
; CHECK-NEXT:    mtvsrd f0, r3
; CHECK-NEXT:    li r3, 8
; CHECK-NEXT:    xxswapd v3, vs0
; CHECK-NEXT:    vspltb v2, v2, 7
; CHECK-NEXT:    lxsibzx v5, r6, r3
; CHECK-NEXT:    vspltb v5, v5, 7
; CHECK-NEXT:    vmrglb v2, v3, v2
; CHECK-NEXT:    vspltb v4, v3, 15
; CHECK-NEXT:    vmrglb v3, v3, v5
; CHECK-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
; CHECK-NEXT:    vmrglh v2, v2, v4
; CHECK-NEXT:    addi r3, r3, .LCPI4_0@toc@l
; CHECK-NEXT:    vmrglw v2, v2, v4
; CHECK-NEXT:    vmrglh v3, v3, v4
; CHECK-NEXT:    vmrglw v3, v4, v3
; CHECK-NEXT:    lxvx v4, 0, r3
; CHECK-NEXT:    li r3, 0
; CHECK-NEXT:    vperm v2, v3, v2, v4
; CHECK-NEXT:    xxspltw v3, v2, 2
; CHECK-NEXT:    vadduwm v2, v2, v3
; CHECK-NEXT:    vextuwrx r3, r3, v2
; CHECK-NEXT:    cmpw cr0, r3, r5
; CHECK-NEXT:    bgelr+ cr0
; CHECK-NEXT:  # %bb.1: # %if.then
;
; P9BE-LABEL: test8:
; P9BE:       # %bb.0: # %entry
; P9BE-NEXT:    add r6, r3, r4
; P9BE-NEXT:    li r7, 8
; P9BE-NEXT:    lxsibzx v2, r6, r7
; P9BE-NEXT:    vspltb v2, v2, 7
; P9BE-NEXT:    lxsibzx v4, r3, r4
; P9BE-NEXT:    li r6, 0
; P9BE-NEXT:    sldi r6, r6, 56
; P9BE-NEXT:    mtvsrd v3, r6
; P9BE-NEXT:    vmrghb v2, v3, v2
; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
; P9BE-NEXT:    vspltb v4, v4, 7
; P9BE-NEXT:    vmrghb v4, v3, v4
; P9BE-NEXT:    vspltb v3, v3, 0
; P9BE-NEXT:    vmrghh v4, v4, v3
; P9BE-NEXT:    xxspltw v3, v3, 0
; P9BE-NEXT:    vmrghw v2, v4, v2
; P9BE-NEXT:    lxvx v4, 0, r3
; P9BE-NEXT:    li r3, 0
; P9BE-NEXT:    vperm v2, v3, v2, v4
; P9BE-NEXT:    xxspltw v3, v2, 1
; P9BE-NEXT:    vadduwm v2, v2, v3
; P9BE-NEXT:    vextuwlx r3, r3, v2
; P9BE-NEXT:    cmpw cr0, r3, r5
; P9BE-NEXT:    bgelr+ cr0
; P9BE-NEXT:  # %bb.1: # %if.then
entry:
  %idxprom = sext i32 %delta to i64
  %add14 = add nsw i32 %delta, 8
  %idxprom15 = sext i32 %add14 to i64
  br label %for.body

for.body:                                         ; preds = %entry
  %arrayidx8 = getelementptr inbounds i8, i8* %sums, i64 %idxprom
  %0 = load i8, i8* %arrayidx8, align 2
  %arrayidx16 = getelementptr inbounds i8, i8* %sums, i64 %idxprom15
  %1 = load i8, i8* %arrayidx16, align 2
  %2 = insertelement <4 x i8> undef, i8 %0, i32 2
  %3 = insertelement <4 x i8> %2, i8 %1, i32 3
  %4 = zext <4 x i8> %3 to <4 x i32>
  %5 = sub nsw <4 x i32> zeroinitializer, %4
  %6 = sub nsw <4 x i32> zeroinitializer, %5
  %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
  %bin.rdx = add <4 x i32> %7, zeroinitializer
  %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
  %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
  %8 = extractelement <4 x i32> %bin.rdx55, i32 0
  %op.extra = add nuw i32 %8, 0
  %cmp25 = icmp slt i32 %op.extra, %thresh
  br i1 %cmp25, label %if.then, label %if.end

if.then:                                          ; preds = %for.body
  unreachable

if.end:                                           ; preds = %for.body
  ret void
}