llvm.org GIT mirror llvm / 14ccc90 test / MC / Disassembler / ARM / unpredictable-LSL-regform.txt
14ccc90

Tree @14ccc90 (Download .tar.gz)

unpredictable-LSL-regform.txt @14ccc90raw · history · blame

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s

# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
#
# A8.6.89 LSL (register)
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;

# CHECK: warning: potentially undefined instruction encoding
0x12 0xf1 0xa0 0xe1